你好，感谢能解决我的问题
C6746在做调试时，通过PLL0 OBSCLK输出管脚测试SYSCLKn时钟频率，写完程序后烧入bin文件后（bin文件下载至Norflash），发现DSP挂了。
之后想通过JTAG恢复，但是无法连接上，显示：
Error connecting to the target:
(Error -1143 @ 0x0)
Device core was hung. The debugger has forced the device to a ready state and recovered debug control, but your application's state is now corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further.
(Emulation package 5.0.747.0)
这里有2个问题：
1、根据datasheet配置，pll0regs->OCSEL = 0x17;pll0regs->OSCDIV = 0x8000 | 4;pll0regs->CKEN = 0x03;
这里的问题不知道出在哪里，是寄存器配置出错，还是时序的问题？
具体代码如下（新增代码加颜色）：
static void DEVICE_PLL0Init()
{
DEVICE_kickUnlock();
CSL_FINST(sys0regs->CFGCHIP0,SYSCFG_CFGCHIP0_PLL_MASTER_LOCK,FREE);//free PLL0
/*step 1: program CLKMODE bit in PLLCTL*/
if(CSL_FEXT(pll0regs->PLLCTL,PLLC_PLLCTL_PLLPWRDN))
{
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_CLKMODE,OSCIN);//use internal clock
}
/*step 2:switch pll to bypass mode
1.clear PLLENSRC bit in PLLCTL
2.select clock source by program EXTCLKSRC bit
3.clear PLLEN bit
4.wait 4 OSC cycles to ensure PLLC switched to bypass mode
*/
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLENSRC,CLEAR);
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_EXTCLKSRC,OSCIN);
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLEN,BYPASS);
// wait for 4 cycles to allow PLLEN mux switches properly to bypass clock
UTIL_waitLoopAccurate (4);
/*step 3: reset PLL by clear PLLRST bit*/
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLRST,ASSERT);//reset PLL
/*step 4: clear PLLPWRDN to 0*/
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLDIS,ASSERT);//disable PLL output
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLPWRDN,POWERED_UP);//power up PLL
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLDIS,DEASSERT);//enable PLL output
/*step 5: program multipler value in PLLM,and POSTDIV(OSCIN=25MHz)*/
CSL_FINS(pll0regs->PLLM,PLLC_PLLM_PLLM,23);//x24,SYSCLK=600MHz
CSL_FINS(pll0regs->POSTDIV,PLLC_POSTDIV_RATIO,1);//divide 2
/*step 6: program PLLnDIV for SYSCLKn
1.Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of PLL)
2.set RATIO for PLLnDIV
3.set GOSET in PLLCMD to 1
4.wait GOSTAT in PLLSTAT to 0(complete of divider)
*/
while(CSL_FEXT(pll0regs->PLLSTAT,PLLC_PLLSTAT_GOSTAT));
CSL_FINS(pll0regs->PLLDIV2,PLLC_PLLDIV2_RATIO,1);//SYSCLK2=150MHz;
CSL_FINS(pll0regs->PLLDIV3,PLLC_PLLDIV3_RATIO,3);//SYSCLK3=75MHz;
CSL_FINS(pll0regs->PLLDIV4,PLLC_PLLDIV4_RATIO,3);//SYSCLK4=75MHz; //rjy_synclk_change mod,2->3
CSL_FINS(pll0regs->PLLDIV7,PLLC_PLLDIV7_RATIO,5);//SYSCLK7=50MHz,this can use for RMII clock;
pll0regs->OCSEL = 0x17;
pll0regs->OSCDIV = 0x8000 | 4;//div 5,(for test PLL clock)
/* Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. */
CSL_FINST(pll0regs->PLLCMD,PLLC_PLLCMD_GOSET,PHASE_ALIGN);
/* Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment). */
while(CSL_FEXT(pll0regs->PLLSTAT,PLLC_PLLSTAT_GOSTAT));
/*step 7:set PLLRST bit to 1(bring PLL out of RESET)*/
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLRST,DEASSERT);
/* Wait for PLL to lock. See PLL spec for PLL lock time */
UTIL_waitLoopAccurate (550);//2000*divide num/sqrt(multiple)
/* Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode */
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLEN,PLL);
pll0regs->CKEN = 0x03;
CSL_FINST(sys0regs->CFGCHIP0,SYSCFG_CFGCHIP0_PLL_MASTER_LOCK,LOCK);//lock PLL0
DEVICE_kickLock();
}
2、如何恢复已经挂的芯片，使用方法
再次感谢！
