[PCIE]关于Application Report “PCIe Use Cases for KeyStone Devices”上的疑问

Assume the DDR destination buffer is located at: 0x8912_5678~0x89D2_5677 (12 MB)

CMD_STATUS[OB_XLT_EN] = 1 (outbound address translation enabled)
Assume OB_SIZE=8 MB (bits [27:23] decide which translation region being used)

Because buffer size (12 MB) is larger than OB_SIZE (8 MB), we must choose two
contiguous translation regions (2*8 MB=16 MB>12 MB) for the transfer. But there is
no limit for which two regions are chosen.

For example, if we choose Region 18 and Region 19 for the translation.
Bits [27:23] = 18 = 10010b --> 0x6900_0000;
Bits [27:23] = 19 = 10011b --> 0x6980_0000;

OB_OFFSET_INDEX18 = 0x7000_0001 (bit [0]=1 enables this region)
(0x7000_0000 is the PCIe address, which can be chosen randomly)
OB_OFFSET18_HI = 0x1234_5678 (64-bit addressing)

OB_OFFSET_INDEX19 = 0x7080_0001
(make Region 19 offset consistent as Region 18, with 8 MB spacing)
OB_OFFSET19_HI = 0x1234_5678

We can use EDMA to do the transfer.
srcAddr = 0x6900_0000;
dstAddr = 0x8912_5678;
dataSize = 12 MB;

The translated address = bits[63:23] of 0x12345678_70000000 + bits[22:0] of
0x6900_0000 = 0x12345678_70000000

Then the data packets with PCIe address
0x12345678_70000000~0x12345678_70BFFFFF (12 MB) will be transferred to the
internal DDR location as 0x8912_5678~0x89D2_5677. The other PCIe device over the
link whose BAR window (64-bit) including this PCIe address range will be the target to
be read from.