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/*use long long type (8 bytes) for MAC address, but only lower 6 bytes are valid. Please note the byte order, MAC address byte 5 is in the lowest bits. Each MAC address corresponding to a Ethernet port*/ unsigned long long Source_MAC_address[GE_NUM_ETHERNET_PORT]= { 0x888888000001, 0x888888000002 }; unsigned long long Dest_MAC_address[GE_NUM_ETHERNET_PORT]= { 0x888888000101, 0x888888000102 };
PHY1 link up. TSCL= 0x4ca7a366 PHY1 link down. TSCL= 0x4caf2502 PHY1 link down. TSCL= 0x4e425de3 PHY1 link down. TSCL= 0x4e821a7b PHY1 link down. TSCL= 0x4e987966 PHY1 link down. TSCL= 0x5064268c PHY1 link down. TSCL= 0x50a19068 PHY1 link down. TSCL= 0x537e53a6 PHY1 link down. TSCL= 0x538e735a PHY1 link down. TSCL= 0x53925894 PHY1 link up. TSCL= 0x53bc054b PHY1 link up. TSCL= 0x53ded48e PHY1 link down. TSCL= 0x5560771b PHY1 link down. TSCL= 0x58d3a5d9 PHY1 link down. TSCL= 0x5907a4c1 PHY1 link up. TSCL= 0x591ff68d
if(gpMDIO_regs->LINK_REG&(1<<uiPhy_NUM)) printf("PHY%d link up. TSCL= 0x%x\n", uiPhy_NUM, TSCL); else printf("PHY%d link down. TSCL= 0x%x\n", uiPhy_NUM, TSCL);
LINK_REG：
MDIO Link state. This register is updated after a read of the Generic Status Register of a PHY. The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, the status of the two PHYs specified in the MDIOUSERPHYSEL registers can be determined using the MLINK input pins. This is determined by the LINKSEL bit in the MDIOUSERPHYSEL register. 0 = The PHY indicates that it does not have a link or fails to acknowledge the read transaction 1 = The PHY with the corresponding address has a link and the PHY acknowledges the read transaction
