DM8168 config 2G

Jimm Miak

Hello Ti friends:

Here i meet a problem when i run load.sh. my config file is .

root@dvr:/opt/dvr_rdk/ti816x_2.8# ./load.sh
Attached to slave procId 2.
Loaded file ../firmware/dvr_rdk_fw_m3vpss.xem3 on slave procId 2.
Started slave procId 2.
After Ipc_loadcallback status [0x00000000]
After Ipc_startcallback status [0x097d2000]
[m3vpss ] ***** SYSTEM : Frequency <ORG> - 250000000, <NEW> - 280000000
[m3vpss ] notify_attach rtnVal 0
[m3vpss ] initProxyServer rtnVal 0
[m3vpss ]
[m3vpss ] *** UTILS: CPU KHz = 560000 Khz ***
[m3vpss ]
[m3vpss ] 43: SYSTEM : System Common Init in progress !!!
Attached to slave procId 1.
Loaded file ../firmware/dvr_rdk_fw_m3video.xem3 on slave procId 1.
Started slave procId 1.
After Ipc_loadcallback status [0x00000000]
After Ipc_startcallback status [0x00000000]
[m3video] ***** SYSTEM : Frequency <ORG> - 250000000, <NEW> - 280000000
[m3video]
[m3video] *** UTILS: CPU KHz = 560000 Khz ***
[m3video]
[m3video] 1355: SYSTEM : System Common Init in progress !!!
Attached to slave procId 0.
Loaded file ../firmware/dvr_rdk_fw_c6xdsp.xe674 on slave procId 0.
Started slave procId 0.
After Ipc_loadcallback status [0x00000000]
[c6xdsp ] ***** SYSTEM : Frequency <ORG> - 800000000, <NEW> - 800000000
[c6xdsp ]
[c6xdsp ] *** UTILS: CPU KHz = 800000 Khz ***
[c6xdsp ]
[c6xdsp ] 5: SYSTEM : System Common Init in progress !!!
After Ipc_startcallback status [0x00000000]
DMA: Module install successful, device major num = 250
DRV: Module install successful
DRV: Module built on Mar 22 2013 10:02:26
111
get bios_cat fail
[c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
[m3video] Remote Debug Shared Memory @ 0xbff05020
[m3vpss ] Remote Debug Shared Memory @ 0xbff0a040
[c6xdsp ] 5634: MEM: Shared Region 2: Base = 0xb1400000, Length = 0x0e500000 (229 MB)
[m3video] 8052: MEM: Shared Region 2: Base = 0xb1400000, Length = 0x0e500000 (229 MB)
[m3vpss ] 8052: MEM: Shared Region 2: Base = 0xb1400000, Length = 0x0e500000 (229 MB)
[c6xdsp ] 5634: MEM: Shared Region 1: Base = 0xc0000000, Length = 0x10000000 (256 MB)
[m3video] 8052: MEM: Shared Region 1: Base = 0xc0000000, Length = 0x10000000 (256 MB)
[m3vpss ] 8052: MEM: Shared Region 1: Base = 0xc0000000, Length = 0x10000000 (256 MB)
[c6xdsp ] 5635: SYSTEM : System Common Init Done !!!
[m3video] 8054: SYSTEM : System Common Init Done !!!
[m3vpss ] 8054: SYSTEM : System Common Init Done !!!
[c6xdsp ] 5499: SYSTEM : System DSP Init in progress !!!
[m3video] 8054: SYSTEM : System Video Init in progress !!!
[m3vpss ] 8054: SYSTEM : System VPSS Init in progress !!!
[c6xdsp ] 5499: SYSTEM : RpeServer_init() done... Ret Val 0!!!
[m3video] 8054: SYSTEM : System Video Init Done !!!
[c6xdsp ] !!WARNING.Resource already registered:2
[c6xdsp ] 5507: SYSTEM : Initializing Links !!!
[m3vpss ] === HDVPSS Clocks are enabled ===
[m3vpss ] === HDVPSS is fully functional ===
[c6xdsp ] 5643: SYSTEM : FREE SPACE : System Heap      = 10268448 B, Mbx = 10240 msgs)
[m3vpss ] === HDVPSS module is not in standby ===
[m3vpss ] === I2C1 Clk is active ===
[c6xdsp ] 5519: SYSTEM : Initializing Links ... DONE !!!
[c6xdsp ] 5519: SYSTEM : System DSP Init Done !!!
[m3video] 8081: HDVICP: Doing PRCM for IVAHD[0] ...
[m3vpss ] 8078: SYSTEM : HDVPSS Drivers Version: HDVPSS_01_00_01_37
[m3video] 8081: HDVICP: PRCM for IVAHD[0] ... DONE.
[m3vpss ] 8078: SYSTEM : FVID2 Init in progress !!!
[m3video] 8081: HDVICP: Doing PRCM for IVAHD[1] ...
[m3video] 8081: HDVICP: PRCM for IVAHD[1] ... DONE.
[m3video] 8081: HDVICP: Doing PRCM for IVAHD[2] ...
[m3video] 8081: HDVICP: PRCM for IVAHD[2] ... DONE.
[m3video] 8082: SYSTEM : Initializing Links !!!
[m3video] 8082: SYSTEM : FREE SPACE : System Heap      = 6280232 B, Mbx = 0 msgs)
[m3video] 8083: SYSTEM : FREE SPACE : SR0 Heap         = 18711424 B (17 MB)
[m3video] 8083: SYSTEM : FREE SPACE : Frame Buffer     = 240123776 B (228 MB)
[m3video] 8083: SYSTEM : FREE SPACE : Bitstream Buffer = 268435328 B (255 MB)
[m3video] 8084: SYSTEM : FREE SPACE : Tiler Buffer     = 0 B (0 MB) - TILER OFF
[m3vpss ] 8131: SYSTEM : FVID2 Init in progress DONE !!!
[m3vpss ] 8131: SYSTEM : Device Init in progress !!!
[m3video] 8107: SYSTEM : Initializing Links ... DONE !!!
[m3vpss ] initPrms.isI2cInitReq = 0
[m3vpss ] initPrms.isI2cInitReq = 0
[m3vpss ] 8134: SYSTEM : Device Init in progress DONE !!!
[m3vpss ] 8255: SYSTEM : System VPSS Init Done !!!
[m3vpss ] 8255: UTILS: DMA: HWI Create for INT62 !!!
[m3vpss ] 8255: SYSTEM : Initializing Links !!!
[m3vpss ] 8255: SYSTEM : FREE SPACE : System Heap      = 13056 B, Mbx = -2 msgs)
[m3vpss ] 8255: SYSTEM : FREE SPACE : SR0 Heap         = 18711424 B (17 MB)
[m3vpss ] 8256: SYSTEM : FREE SPACE : Frame Buffer     = 235813760 B (224 MB)
[m3vpss ] 8256: SYSTEM : FREE SPACE : Bitstream Buffer = 268435328 B (255 MB)

it's pause forever.

who can help me? thanks for any help.

12 年多前

0 Jimm Miak 12 年多前

Prodigy 40 points

/*
* ======== config.bld ========
* Build configuration script for HDVPSS drivers
*/

/* load the required modules for the configuration */

var M3 = xdc.useModule('ti.targets.arm.elf.M3');
var C674 = xdc.useModule('ti.targets.elf.C674');

var buildReleaseConfig = true;

/* configure the options for the M3 targets */

/* M3 compiler directory path */
M3.rootDir = java.lang.System.getenv("CGTOOLS");

/* linker options */

M3.lnkOpts.suffix += " --zero_init=off ";
M3.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";

/* compiler options */
M3.ccOpts.suffix += " --gcc -DTI_816X_BUILD -DPLATFORM_EVM_SI -DSYSLINK_BUILD_RTOS -DUSE_SYSLINK_NOTIFY=0 -DUTILS_ASSERT_ENABLE";

/* set default platform and list of all interested
* platforms for M3
*/
M3.platforms = [
                        "ti.platforms.evmTI816X:core0",
                        "ti.platforms.evmTI816X:core1",
               ];

/* Select the default platform
*
* Making core1 as defualt core configuration to be used
* Core 0 == Ducati.M3.VIDEO
* Core 1 == Ducati.M3.VPS
*/
M3.platform = M3.platforms[1];

/* configure the options for the C674 targets */

/* C674 compiler directory path */
C674.rootDir = java.lang.System.getenv("CGTOOLS_DSP");

/* linker options */

C674.lnkOpts.suffix += " --zero_init=off ";
C674.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";

/* compiler options */
C674.ccOpts.suffix += " -DTI_816X_BUILD -DPLATFORM_EVM_SI -DSYSLINK_BUILD_RTOS -DUSE_SYSLINK_NOTIFY=0";

C674.platforms = ["ti.platforms.evmTI816X:plat"];
C674.platform = C674.platforms[0];

/* list interested targets in Build.targets array */
Build.targets = [
                    M3,
                    C674,
                ];

Memory Map - 2GB DDR

+-0x80000000-+   +-------------------+
         ^       |                   |
         |       |   128 MB          | Linux
         |       |                   |
         |       +-------------------+
         |       |                   |
     |       | 337.5 MB         | (SR1) Bitstream buffer
         |       |                   | Cached on A8. Cached on M3, although access by DMAs
         |       |                   |
         |       +-------------------+
      | |   1   MB          | (SR3)InterDucati IPC ListMP .Cached on M3
      | +-------------------+
         +       |   2.5 MB          | Video M3 Code
       512 MB    +-------------------+
         +       |   10 MB           | Video M3 Data
         |       +-------------------+
         |       |   2   MB          | VPSS M3 Code
         |       +-------------------+
         |       |   15.5 MB         | VPSS M3 Data
         |       +-------------------+
         |       |   1.5 MB          | DSP Code
         |       +-------------------+
         v       |   14 MB          | DSP Data
+-0xA0000000-+   +-------------------+
         ^       |   128 MB          | Tiled 8-bit region
         |       |                   |
         |       +-------------------+
         |       |   128 MB          | Tiled 16-bit region
         |       |                   |
         |       +-------------------+
         |       |                   |
         |       |                   |
         +       | 233 MB           | (SR2) Frame Buffer Region
       512 MB    |                   | VPSS - Video M3 Frame Buf
         +       |                   |
         |       +-------------------+
         |       | 16 MB           | (SR0) Syslink MsgQ/IPC List MP
         |       |                   | Non-cached on M3
         |       +-------------------+
         |       | 2    MB          | VPSS M3 - VPDMA Descriptor
         |       +-------------------+
         |       | 2    MB          | VPSS M3 - FBDev Shared Memory
         |       +-------------------+
         |       | 2    MB          | Host - VPSS M3 Notify(For FBDev)
         |       +-------------------+
         v       | 1    MB          | Remote Debug Print
+-0xC0000000-+   +-------------------+
         ^       |                   |
         |       |                   |
         |       |                   |
         |       |                   |
         |       |                   |
         |       |                   |
         +       |                   |
       1024 MB   | 1024 MB          | Memory for Linux Kernel
         +       |                   | Available only in 2G-2G Split of linux kernel
         |       |                   |
         |       |                   |
         |       |                   |
         |       |                   |
         v       |                   |
+-0xFFFFFFFF-+   +-------------------+

var KB=1024;
var MB=KB*KB;

var DDR3_ADDR;
var DDR3_SIZE;

var OCMC0_ADDR;
var OCMC1_ADDR;
var OCMC_SIZE;

var LINUX_ADDR;
var LINUX_SIZE;

var SR0_ADDR;
var SR0_SIZE;

var SR1_ADDR;
var SR1_SIZE;

var SR3_INTRADUCATI_IPC_ADDR;
var SR3_INTRADUCATI_IPC_SIZE;

var VIDEO_M3_CODE_ADDR;
var VIDEO_M3_CODE_SIZE;

var VIDEO_M3_DATA_ADDR;
var VIDEO_M3_DATA_SIZE;

var SR2_FRAME_BUFFER_ADDR;
var SR2_FRAME_BUFFER_SIZE;

var DSS_M3_CODE_ADDR;
var DSS_M3_CODE_SIZE;

var DSS_M3_DATA_ADDR;
var DSS_M3_DATA_SIZE;

var DSP_CODE_ADDR;
var DSP_CODE_SIZE;

var DSP_M3_DATA_ADDR;
var DSP_M3_DATA_SIZE;

var TILER_ADDR;
var TILER_SIZE;

var HDVPSS_DESC_ADDR;
var HDVPSS_DESC_SIZE;

var HDVPSS_SHARED_ADDR;
var HDVPSS_SHARED_SIZE;

var NOTIFY_SHARED_ADDR;
var NOTIFY_SHARED_SIZE;

var REMOTE_DEBUG_ADDR;
var REMOTE_DEBUG_SIZE;

DDR3_ADDR = 0x80000000;
DDR3_SIZE = 2048*MB;

OCMC0_ADDR                 = 0x40300000;
OCMC1_ADDR                 = 0x40400000;
OCMC0_RUN_ADDR             = 0x00300000;
OCMC1_RUN_ADDR             = 0x00400000;
OCMC_SIZE                  = 256*KB;

L2_SRAM_ADDR               = 0x55024000;
L2_SRAM_SIZE               = 128*KB;
L2_SRAM_RUN_ADDR           = 0x20004000;

DUCATI_WB_WA_ADDR = 0x20000000;

print("I will compile 2G bld\n");

/* first 512MB */
LINUX_SIZE                 = 460*MB;
VIDEO_M3_CODE_SIZE         = 2.5*MB;
VIDEO_M3_DATA_SIZE         = 9.5*MB;
DSS_M3_CODE_SIZE           = 2*MB;
DSS_M3_DATA_SIZE           = 15.5*MB;
DSP_CODE_SIZE              = 1.5*MB;
DSP_DATA_SIZE              = 21*MB;

/* second 512MB */
TILER_SIZE                 = 256*MB; /* (128+128) - MUST be aligned on 128MB boundary */
SR0_SIZE                   = 20*MB;
SR2_FRAME_BUFFER_SIZE      = 229*MB;
HDVPSS_DESC_SIZE           = 2*MB;
HDVPSS_SHARED_SIZE         = 2*MB;
NOTIFY_SHARED_SIZE         = 2*MB;
REMOTE_DEBUG_SIZE          = 1*MB;

/* third and fourth 512 MB */
SR1_SIZE                   = 256*MB;
SR3_INTRADUCATI_IPC_SIZE   = 1*MB;
LINUX_SIZE_SEGMENT2        = 758*MB;

/* first 512MB */
LINUX_ADDR                 = DDR3_ADDR;
VIDEO_M3_CODE_ADDR         = LINUX_ADDR   + LINUX_SIZE;
VIDEO_M3_DATA_ADDR         = VIDEO_M3_CODE_ADDR         + VIDEO_M3_CODE_SIZE;
DSS_M3_CODE_ADDR           = VIDEO_M3_DATA_ADDR         + VIDEO_M3_DATA_SIZE;
DSS_M3_DATA_ADDR           = DSS_M3_CODE_ADDR           + DSS_M3_CODE_SIZE;
DSP_CODE_ADDR              = DSS_M3_DATA_ADDR           + DSS_M3_DATA_SIZE;
DSP_DATA_ADDR              = DSP_CODE_ADDR              + DSP_CODE_SIZE;

/* second 512MB */
TILER_ADDR                 =DSP_DATA_ADDR       + DSP_DATA_SIZE;
SR0_ADDR                   = TILER_ADDR              + TILER_SIZE;
SR2_FRAME_BUFFER_ADDR      = SR0_ADDR + SR0_SIZE;
HDVPSS_DESC_ADDR           = SR2_FRAME_BUFFER_ADDR      + SR2_FRAME_BUFFER_SIZE;
HDVPSS_SHARED_ADDR         = HDVPSS_DESC_ADDR           + HDVPSS_DESC_SIZE;
NOTIFY_SHARED_ADDR         = HDVPSS_SHARED_ADDR         + HDVPSS_SHARED_SIZE;
REMOTE_DEBUG_ADDR          = NOTIFY_SHARED_ADDR         + NOTIFY_SHARED_SIZE;

/* second 512MB */
SR1_ADDR = REMOTE_DEBUG_ADDR+REMOTE_DEBUG_SIZE;
SR3_INTRADUCATI_IPC_ADDR = SR1_ADDR + SR1_SIZE;

Build.platformTable["ti.platforms.evmTI816X:core1"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len: DDR3_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len: OCMC_SIZE
        }],
    ],
    customMemoryMap:
    [
        ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["VIDEO_M3_DATA_MEM", {
            comment : "VIDEO_M3_DATA_MEM",
            name    : "VIDEO_M3_DATA_MEM",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DDR3_M3", {
            comment : "DDR3_M3",
            name    : "DDR3_M3",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["DSP_CODE_MEM", {
            comment : "DSP_CODE_MEM",
            name    : "DSP_CODE_MEM",
            base    : DSP_CODE_ADDR,
            len     : DSP_CODE_SIZE
        }],
        ["DSP_DATA_MEM", {
            comment : "DDR3_DSP",
            name    : "DDR3_DSP",
            base    : DSP_DATA_ADDR,
            len     : DSP_DATA_SIZE
        }],
        ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["SR3_INTRADUCATI_IPC", {
            comment : "SR3_INTRADUCATI_IPC",
            name    : "SR3_INTRADUCATI_IPC",
            base    : SR3_INTRADUCATI_IPC_ADDR,
            len     : SR3_INTRADUCATI_IPC_SIZE
        }],
        ["L2_ROM", {
            comment: "L2_ROM",
            name: "L2_ROM",
            base: 0x00000000,
            len: 0x00004000
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len: OCMC_SIZE
        }],
        ["OCMC1_RAM_MAPPED", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM_MAPPED",
            base: OCMC1_RUN_ADDR,
            len: OCMC_SIZE
        }],
    ]
};

Build.platformTable["ti.platforms.evmTI816X:core0"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len: DDR3_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len: OCMC_SIZE
        }],
        ["L2_SRAM", {
            comment: "L2_SRAM",
            name: "L2_SRAM",
            base: L2_SRAM_ADDR,
            len: L2_SRAM_SIZE
        }],
        ["L2_SRAM_RUN", {
            comment: "L2_SRAM_RUN",
            name: "L2_SRAM_RUN",
            base: L2_SRAM_RUN_ADDR,
            len: L2_SRAM_SIZE
        }],
    ],
    customMemoryMap:
    [
               ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["VIDEO_M3_DATA_MEM", {
            comment : "VIDEO_M3_DATA_MEM",
            name    : "VIDEO_M3_DATA_MEM",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DDR3_M3", {
            comment : "DDR3_M3",
            name    : "DDR3_M3",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["DSP_CODE_MEM", {
            comment : "DSP_CODE_MEM",
            name    : "DSP_CODE_MEM",
            base    : DSP_CODE_ADDR,
            len     : DSP_CODE_SIZE
        }],
        ["DSP_DATA_MEM", {
            comment : "DDR3_DSP",
            name    : "DDR3_DSP",
            base    : DSP_DATA_ADDR,
            len     : DSP_DATA_SIZE
        }],
        ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["SR3_INTRADUCATI_IPC", {
            comment : "SR3_INTRADUCATI_IPC",
            name    : "SR3_INTRADUCATI_IPC",
            base    : SR3_INTRADUCATI_IPC_ADDR,
            len     : SR3_INTRADUCATI_IPC_SIZE
        }],
        ["L2_SRAM", {
            comment: "L2_SRAM",
            name: "L2_SRAM",
            base: L2_SRAM_ADDR,
            len: L2_SRAM_SIZE
        }],
        ["L2_SRAM_RUN", {
            comment: "L2_SRAM_RUN",
            name: "L2_SRAM_RUN",
            base: L2_SRAM_RUN_ADDR,
            len: L2_SRAM_SIZE
        }],
        ["L2_ROM", {
            comment: "L2_ROM",
            name: "L2_ROM",
            base: 0x00000000,
            len: 0x00004000
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len: OCMC_SIZE
        }],
        ["OCMC0_RAM_MAPPED", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM_MAPPED",
            base: OCMC0_RUN_ADDR,
            len: OCMC_SIZE
        }],
    ]
};

Build.platformTable["ti.platforms.evmTI816X:plat"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len: DDR3_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len: OCMC_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len: OCMC_SIZE
        }],
    ],
    customMemoryMap:
    [
          ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["VIDEO_M3_DATA_MEM", {
            comment : "VIDEO_M3_DATA_MEM",
            name    : "VIDEO_M3_DATA_MEM",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DDR3_M3", {
            comment : "DDR3_M3",
            name    : "DDR3_M3",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["DSP_CODE_MEM", {
            comment : "DSP_CODE_MEM",
            name    : "DSP_CODE_MEM",
            base    : DSP_CODE_ADDR,
            len     : DSP_CODE_SIZE
        }],
        ["DSP_DATA_MEM", {
            comment : "DDR3_DSP",
            name    : "DDR3_DSP",
            base    : DSP_DATA_ADDR,
            len     : DSP_DATA_SIZE
        }],
        ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["SR3_INTRADUCATI_IPC", {
            comment : "SR3_INTRADUCATI_IPC",
            name    : "SR3_INTRADUCATI_IPC",
            base    : SR3_INTRADUCATI_IPC_ADDR,
            len     : SR3_INTRADUCATI_IPC_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len: OCMC_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len: OCMC_SIZE
        }],
        ["DSP_L2_RAM", {
            comment: "DSP_L2_RAM",
            name: "DSP_L2_RAM",
            base: 0x10800000,
            len: 0x00020000
        }],
    ],
    l1PMode: "32k",
    l1DMode: "32k",
    l2Mode: "128k"
};

var addrFileGenerated = false;
if (addrFileGenerated == false)
{
xdc.loadCapsule("genaddrinfo.xs").GenAddrFile();
addrFileGenerated = true;
}

config_2G.bld file.

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DM8168 config 2G