如何调试OMAP3530ARM这一端，如何配置一个GPIO口为接受输入中断模式？

PAD_CONF 寄存器中先将引脚设GPIO

然后再GPIO_IRQENABLE设置引脚的中断使能

这个是所有的么，那上升沿触发还是下降沿这些都不明确啊 ， 只用设置这两个么？

或者你帮我看看这篇文章问题出在哪里？

All,

I currently have an issue setting up an interrupt on the OMAP 3530 IVA module(a.k.a DSP) . I am trying to use GPIO 22 and 23 for the interrupt. I first configure the appropriate padconfig register to Mux_Mode_4 and input enable

// gpio 22

pSTBCtx->Hardware_Context.pPadConfig->CONTROL_PADCONF_ETK_D8=(MUX_MODE_4|INPUT_ENABLE);

// gpio 23

pSTBCtx->Hardware_Context.pPadConfig->CONTROL_PADCONF_ETK_D9=(MUX_MODE_4|INPUT_ENABLE);

I then setup the bank 1 registers as shown below

#define GPIO_22_BIT_OFFSET  (1<<22)

#define GPIO_23_BIT_OFFSET  (1<<23)

#define SCHEDULE_REQUEST GPIO_22_BIT_OFFSET

#define COLLECTION_DONE GPIO_23_BIT_OFFSET

pSTBCtx->Hardware_Context.pBank1->OE|=SCHEDULE_REQUEST|COLLECTION_DONE;

pSTBCtx->Hardware_Context.pBank1->RISINGDETECT|=SCHEDULE_REQUEST|COLLECTION_DONE ;

pSTBCtx->Hardware_Context.pBank1->SETIRQENABLE2=SCHEDULE_REQUEST ;

pSTBCtx->Hardware_Context.pBank1->SETIRQENABLE2=COLLECTION_DONE ;

At this point I see the following in the Bank registers.

pBank1 0x48310000 OMAP_GPIO_REGS * hex NotEdited

REVISION 0x00000025 REG32 hex NotEdited

zzzReserved01 0x48310004 unsigned int[3] hex NotEdited

SYSCONFIG 0x00000015 REG32 hex NotEdited

SYSSTATUS 0x00000001 REG32 hex NotEdited

IRQSTATUS1 0x00400000 REG32 hex NotEdited

IRQENABLE1 0x00000000 REG32 hex NotEdited

WAKEUPENABLE 0x00000000 REG32 hex NotEdited

RESERVED_0024 0x00000000 REG32 hex NotEdited

IRQSTATUS2 0x00400000 REG32 hex NotEdited

IRQENABLE2 0x00C00000 REG32 hex NotEdited

CTRL 0x00000000 REG32 hex NotEdited

OE 0xFFDE3FFF REG32 hex NotEdited

DATAIN 0x000100BC REG32 hex NotEdited

DATAOUT 0x00010000 REG32 hex NotEdited

LEVELDETECT0 0x00000000 REG32 hex NotEdited

LEVELDETECT1 0x00000000 REG32 hex NotEdited

RISINGDETECT 0x00C00000 REG32 hex NotEdited

FALLINGDETECT 0x00000000 REG32 hex NotEdited

DEBOUNCENABLE 0x00000000 REG32 hex NotEdited

DEBOUNCINGTIME 0x00000000 REG32 hex NotEdited

zzzReserved02 0x48310058 unsigned int[2] hex NotEdited

CLEARIRQENABLE1 0x00000000 REG32 hex NotEdited

SETIRQENABLE1 0x00000000 REG32 hex NotEdited

zzzReserved03 0x48310068 unsigned int[2] hex NotEdited

CLEARIRQENABLE2 0x00C00000 REG32 hex NotEdited

SETIRQENABLE2 0x00C00000 REG32 hex NotEdited

zzzReserved04 0x48310078 unsigned int[2] hex NotEdited

CLEARWAKEUPENA 0x00000000 REG32 hex NotEdited

SETWAKEUPENA 0x00000000 REG32 hex NotEdited

zzzReserved05 0x48310088 unsigned int[2] hex NotEdited

CLEARDATAOUT 0x00010000 REG32 hex NotEdited

SETDATAOUT 0x00010000 REG32 hex NotEdited

zzzReserved06 0x48310098 unsigned int[2] hex NotEdited

As you can see the IRQSTATUS2 indicates that the GPIO 22 has triggered.

I now enable the Wugen with following call

#define EVENT_ID_BANK_1 73

HWI_enableWugen(EVENT_ID_BANK_1);

I read the  WUGEN_MEVTSET1 register below:

0xEFFFFFFF

This indicates that IRQ 28  is unmasked(I think). However when I read the WUGEN_PENDEVT0 register. I get:

0x00008000

I think the value should be 0x1xxxxxxx.

I then map the event to an interrupt:

#define HWINT_BANK6 7

HWI_eventMap(HWINT_BANK6,EVENT_ID_BANK_1);

I then Plug the ISR

//The ISR needs to be plugged

HWI_dispatchPlug(HWINT_BANK6,Gpio_Bank6_ISR,-1,NULL);

Finally I enable the IER

//The corresponding IER bit needs to be enabled.

C64_enableIER(1<<HWINT_BANK6);

But I never see the ISR get called and the corresponding bit in the IFR never gets set.

Any ideas?

Thanks,

Ram

设置电平触发为GPIODETECT1 和GPIODETECT2

上升沿触发为RISINGDETECT

下降沿触发为FALLENDETECT

这些在Technical Reference Guide里都有的

我要的是完整的配置过程，可以响应来自外中断的配置方式，包括GPIO的焊版，输入输出模式，上升沿还是下降沿检测，中断使能，不是你这种随随便便挑两点讲，请给一个完整的配置方案好么？

嘻嘻 谢谢大牛，早知道你就是嫌麻烦，不想写，呵呵，这个论坛真的好棒，三寸丁好人。呵呵

嘻嘻 谢谢大牛，早知道你就是嫌麻烦，不想写，呵呵，这个论坛真的好棒，三寸丁好人。呵呵

你好我想问一下，注册中断的中断号怎么给