Other Parts Discussed in Thread: MATHLIB, SYSBIOS
TI的工程师，您好！
我在使用DSP核触发定时器的时候，发现了定时器中断的周期并不精准，情况如下：
1、在定时器中断回调中调用IO口翻转，进入中断时将IO口拉高，退出中断时将IO口拉低，IO翻转之间运行一些浮点计算，通过观察高电平持续时间来确定浮点运算的时间
2、测试的波形：
可以看出，高电平持续的时间很不稳定，但我没有打开其它任何的中断，也没有任何的任务运行
3、我在浮点运算结束后调用一个没用的函数，而定时器的稳定性取决于这个没用的函数处于哪个.c源文件里面，当放在main.c文件中时，定时器触发高电平持续时间的波动较小，当放在其它.c文件中时，波动较大（放在不同的文件中编译出的.out文件大小不一致，放在main.c编译出的.out文件大小较小，我怀疑与.out文件大小有关，但有时.out大小为5000Kb反而比4600Kb更为稳定一点）。
4、没用的函数：
uint8_t testCheckReady(void)
{
uint8_t u8Ret = 0;
if (0 == u8Ret)
{
u8Ret = 1;
return u8Ret;
}
return u8Ret;
}
5、浮点运算函数：
void realtimeTestFxn(float *value)
{
int testcnt = 0;
float testfvalue1 = 3;
for (testcnt = 0; testcnt < 420; ++testcnt)
{
testfvalue1 = (testfvalue1 / 0.6537 + testfvalue1) * 0.3538 - (testfvalue1 / 13.2354);
}
*value = testfvalue1;
u8Status = testCheckReady();
if (0 != u8Status)
return;
}
6、测试源文件：
/* XDCtools Header files */
#include <xdc/std.h>
#include <xdc/cfg/global.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/Diags.h>
#include <xdc/runtime/Log.h>
#include <xdc/runtime/Assert.h>
#include <xdc/runtime/Registry.h>
#include <xdc/runtime/IHeap.h>
#include <xdc/runtime/Memory.h>
/* BIOS Header files */
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Clock.h>
#include <ti/sysbios/heaps/HeapMem.h>
#include <ti/sysbios/hal/Hwi.h>
#include <ti/sysbios/knl/Swi.h>
#include <ti/ipc/Ipc.h>
#include <ti/ipc/MessageQ.h>
#include <ti/ipc/GateMP.h>
#include <ti/ipc/MultiProc.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <ti/sysbios/knl/Queue.h>
#include <ti/sysbios/knl/Mailbox.h>
#include <stdio.h>
#include <ti/csl/example/utils/common/inc/app_utils.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/csl_edma.h>
#include <ti/csl/arch/csl_arch.h>
/* TI-RTOS Header files */
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/drv/gpio/test/led_blink/src/GPIO_log.h>
#include <ti/drv/gpio/test/led_blink/src/GPIO_board.h>
#include <ti/board/board.h>
#include <idkam571x_pinmux.h>
#include <ti/osal/osal.h>
#include <ti/osal/CacheP.h>
/* SPI Header files */
#include <ti/drv/spi/SPI.h>
#include <ti/csl/csl_mcspi.h>
#include <ti/drv/spi/soc/SPI_soc.h>
#include <ti/drv/spi/src/SPI_osal.h>
extern void TimerFxn(UArg arg);
extern void TimerTick(UArg arg);
extern uint8_t testCheckReady(void);
uint8_t testCheckReady(void)
{
uint8_t u8Ret = 0;
if (0 == u8Ret)
{
u8Ret = 1;
return u8Ret;
}
return u8Ret;
}
float testrealtimevalue = 0;
void realtimeTestFxn(float *value)
{
int testcnt = 0;
float testfvalue1 = 3;
for (testcnt = 0; testcnt < 420; ++testcnt)
{
testfvalue1 = (testfvalue1 / 0.6537 + testfvalue1) * 0.3538
- (testfvalue1 / 13.2354);
}
*value = testfvalue1;
u8Status = testCheckReady();
if (0 != u8Status)
return;
}
/*
* ======== main ========
*/
int main(void)
{
Task_Handle task;
Task_Params params;
Error_Block eb;
Error_init(&eb);
PinmuxGpioConfig();
GPIO_init();
BIOS_start();
return (0);
}
void TimerClock_Tick(UArg arg)
{
static unsigned int clkcnt = 0;
if (clkcnt++ >= arg)
{
clkcnt = 0;
Clock_tick();
}
}
void TimerTick(UArg arg)
{
Clock_tick();
}
void TimerFxn(UArg arg)
{
GPIO_write(0, GPIO_PIN_VAL_HIGH); //高电平
float tmpvalue = 0;
realtimeTestFxn(&tmpvalue);
testrealtimevalue = tmpvalue;
GPIO_write(0, GPIO_PIN_VAL_LOW); //低电平
}
7、cfg文件：
//BWC, add Program var
/* root of the configuration object model */
var Program = xdc.useModule('xdc.cfg.Program');
/* ================ General configuration ================ */
var Memory = xdc.useModule('xdc.runtime.Memory');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
var Log = xdc.useModule('xdc.runtime.Log');
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
var ECM = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
var System = xdc.useModule('xdc.runtime.System');
SysStd = xdc.useModule('xdc.runtime.SysStd');
var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
var halCache = xdc.useModule('ti.sysbios.hal.Cache');
var Idle = xdc.useModule('ti.sysbios.knl.Idle');
var Deh = xdc.useModule('ti.deh.Deh');
var Timer = xdc.useModule('ti.sysbios.hal.Timer');
var Clock = xdc.useModule('ti.sysbios.knl.Clock');
var ti_sysbios_timers_dmtimer_Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
var Event = xdc.useModule('ti.sysbios.knl.Event');
var Mailbox = xdc.useModule('ti.sysbios.knl.Mailbox');
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
//var ti_sysbios_timers_timer64_Timer = xdc.useModule('ti.sysbios.timers.timer64.Timer');
//var ti_sysbios_timers_gptimer_Timer = xdc.useModule('ti.sysbios.timers.gptimer.Timer');
/* application uses the following modules and packages */
xdc.useModule('xdc.runtime.Assert');
xdc.useModule('xdc.runtime.Error');
/* Must be placed before pwr mgmt */
Idle.addFunc('&ti_deh_Deh_idleBegin');
System.SupportProxy = SysStd;
/*
* Enable Event Groups here and registering of ISR for specific GEM INTC is done
* using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs
*/
var exception = xdc.useModule('ti.sysbios.family.c64p.Exception');
exception.enablePrint = false;
/* ================ BIOS configuration ================ */
var BIOS = xdc.useModule('ti.sysbios.BIOS');
/* Enable BIOS Task Scheduler */
BIOS.taskEnabled = true;
BIOS.heapSize = 0x200000;
BIOS.heapSection = "systemHeap";
BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');
/* ================ Task configuration ================ */
/* No runtime stack checking is performed */
Task.checkStackFlag = true;
/* Reduce the number of task priorities */
Task.numPriorities = 16;
Task.common$.namedInstance = true;
/* ================ Driver configuration ================ */
/*use CSL package*/
var socType = "am571x";
var Csl = xdc.loadPackage('ti.csl');
Csl.Settings.deviceType = socType;
/* Load the OSAL package */
var osType = "tirtos"
var Osal = xdc.useModule('ti.osal.Settings');
Osal.osType = osType;
Osal.socType = socType;
/* Load the gpio package */
var GPIO = xdc.loadPackage('ti.drv.gpio');
GPIO.Settings.socType = socType;
/* Load the I2C package */
var I2c = xdc.loadPackage('ti.drv.i2c');
/* Load the Board package and set the board name */
var Board = xdc.loadPackage('ti.board');
Board.Settings.boardName = "idkAM571x";
/* root of the configuration object model */
var Program = xdc.useModule('xdc.cfg.Program');
/* load the configuration shared across cores */
Program.global.procName = "DSP1";
Program.sectMap[".tracebuf"] = "TRACE_BUF";
Program.sectMap[".errorbuf"] = "EXC_DATA";
Program.sectMap[".l2sram"] = "L2SRAM";
/*
* ======== IPC Configuration ========
*/
xdc.useModule('ti.ipc.ipcmgr.IpcMgr');
var ipc_cfg = xdc.loadCapsule("ipc.cfg.xs");
/*
* ======== SYS/BIOS Configuration ========
*/
if (Program.build.profile == "debug")
{
BIOS.libType = BIOS.LibType_Debug;
}
else
{
BIOS.libType = BIOS.LibType_Custom;
}
/* create a heap for MessageQ messages */
//var params = new HeapBuf.Params;
//params.align = 8;
//params.blockSize = 512;
//params.numBlocks = 256;
//var msgHeap = HeapBuf.create(params);
var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
//MessageQ.registerHeapMeta(msgHeap, 0);
/* Setup MessageQ transport */
var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
MessageQ.SetupTransportProxy = VirtioSetup;
/* Setup NameServer remote proxy */
var NameServer = xdc.useModule("ti.sdo.utils.NameServer");
var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
NameServer.SetupProxy = NsRemote;
/* Enable Memory Translation module that operates on the BIOS Resource Table */
var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
Resource.loadSegment = "EXT_CODE";
Resource.customTable = true;
/* Use SysMin because trace buffer address is required for Linux/QNX
* trace debug driver, plus provides better performance.
*/
var System = xdc.useModule('xdc.runtime.System');
var SysMin = xdc.useModule('ti.trace.SysMin');
System.SupportProxy = SysMin;
SysMin.bufSize = 0x8000;
/*
* ======== Instrumentation Configuration ========
*/
/* system logger */
var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
var LoggerSysParams = new LoggerSys.Params();
var Defaults = xdc.useModule('xdc.runtime.Defaults');
Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
/* enable runtime Diags_setMask() for non-XDC spec'd modules */
var Diags = xdc.useModule('xdc.runtime.Diags');
Diags.setMaskEnabled = true;
/* override diags mask for selected modules */
xdc.useModule('xdc.runtime.Main');
Diags.setMaskMeta("xdc.runtime.Main",
Diags.ENTRY | Diags.EXIT | Diags.INFO, Diags.RUNTIME_ON);
var Registry = xdc.useModule('xdc.runtime.Registry');
Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF;
Registry.common$.diags_EXIT = Diags.RUNTIME_OFF;
Registry.common$.diags_INFO = Diags.RUNTIME_OFF;
Registry.common$.diags_USER1 = Diags.RUNTIME_OFF;
Registry.common$.diags_LIFECYCLE = Diags.RUNTIME_OFF;
Registry.common$.diags_STATUS = Diags.RUNTIME_OFF;
var Main = xdc.useModule('xdc.runtime.Main');
Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
/* Override the default resource table with my own */
var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
Resource.customTable = true;
var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
TimerSupport.availMask = 0xFFFF;
/*ti_sysbios_timers_dmtimer_Timer.timerSettings[4].intNum = 4;
var timer0Params = new Timer.Params();
timer0Params.instance.name = "timer0";
timer0Params.period = 10;
timer0Params.periodType = xdc.module("ti.sysbios.interfaces.ITimer").PeriodType_MICROSECS;
timer0Params.extFreq.lo = 20000000;
timer0Params.runMode = xdc.module("ti.sysbios.interfaces.ITimer").RunMode_CONTINUOUS;
timer0Params.arg = 100;
Program.global.timer0 = Timer.create(4, "&TimerFxn", timer0Params);*/
/*ti_sysbios_timers_dmtimer_Timer.timerSettings[12].intNum = 13;
var timer1Params = new Timer.Params();
timer1Params.instance.name = "timer1";
timer1Params.period = 1000;
timer1Params.periodType = xdc.module("ti.sysbios.interfaces.ITimer").PeriodType_MICROSECS;
timer1Params.extFreq.lo = 20000000;
timer1Params.runMode = xdc.module("ti.sysbios.interfaces.ITimer").RunMode_CONTINUOUS;
timer1Params.arg = 0;
Program.global.timer1 = Timer.create(12, "&TimerTick", timer1Params);*/
Clock.tickSource = Clock.TickSource_USER;
Clock.tickPeriod = 1000;
/* ================ Driver configuration ================ */
var drv = xdc.loadPackage ("ti.sdo.edma3.drv");
var rm = xdc.loadPackage ("ti.sdo.edma3.rm");
var rm = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
BIOS.cpuFreq.lo = 700000000;
//ECM.eventGroupHwiNum[0] = 7;
//ECM.eventGroupHwiNum[1] = 8;
//ECM.eventGroupHwiNum[2] = 9;
//ECM.eventGroupHwiNum[3] = 10;
//BIOS.addUserStartupFunction('&IpcMgr_callIpcStart');
/* describe the processors in the system */
//var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
//MultiProc.setConfig("DSP1", ["HOST", "IPU2", "IPU1", "DSP2", "DSP1"]);
/* GateMP host support */
//var GateMP = xdc.useModule('ti.sdo.ipc.GateMP');
//GateMP.hostSupport = true;
/* shared region configuration */
//var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
/* configure SharedRegion #0 (IPC) */
/*var SR0Mem = Program.cpu.memoryMap["SR_0"];
SharedRegion.setEntryMeta(0,
new SharedRegion.Entry({
name: "SR0",
base: SR0Mem.base,
len: SR0Mem.len,
ownerProcId: MultiProc.getIdMeta("DSP1"),
cacheEnable: true,
isValid: true
})
);
xdc.useModule('ti.sysbios.xdcruntime.GateThreadSupport');
var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');*/
//var Mathlib = xdc.useModule("ti.mathlib.Version");
//var MessageQ_SetupTransportProxy = xdc.module('ti.sdo.ipc.MessageQ_SetupTransportProxy');
//MessageQ_SetupTransportProxy.priority = 14;
var ti_sysbios_timers_dmtimer_Timer0Params = new ti_sysbios_timers_dmtimer_Timer.Params();
ti_sysbios_timers_dmtimer_Timer0Params.instance.name = "ti_sysbios_timers_dmtimer_Timer0";
ti_sysbios_timers_dmtimer_Timer0Params.period = 10;
ti_sysbios_timers_dmtimer_Timer0Params.extFreq.lo = 20000000;
ti_sysbios_timers_dmtimer_Timer0Params.arg = 100;
Program.global.ti_sysbios_timers_dmtimer_Timer0 = ti_sysbios_timers_dmtimer_Timer.create(4, "&TimerFxn", ti_sysbios_timers_dmtimer_Timer0Params);
ti_sysbios_timers_dmtimer_Timer.timerSettings[4].intNum = 4;
ti_sysbios_timers_dmtimer_Timer.timerSettings[5].intNum = 5;
ti_sysbios_timers_dmtimer_Timer.timerSettings[13].intNum = 6;
ti_sysbios_timers_dmtimer_Timer.timerSettings[12].intNum = 7;
var ti_sysbios_timers_dmtimer_Timer1Params = new ti_sysbios_timers_dmtimer_Timer.Params();
ti_sysbios_timers_dmtimer_Timer1Params.instance.name = "ti_sysbios_timers_dmtimer_Timer1";
ti_sysbios_timers_dmtimer_Timer1Params.period = 1000;
Program.global.ti_sysbios_timers_dmtimer_Timer1 = ti_sysbios_timers_dmtimer_Timer.create(12, "&TimerTick", ti_sysbios_timers_dmtimer_Timer1Params);
8、bld文件：
/*
* Copyright (c) 2013-2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== config.bld ========
*
*/
var Build = xdc.useModule('xdc.bld.BuildEnvironment');
var evmDRA7XX_EDMA = {
name: "EDMA", space: "data", access: "RWX",
base: 0x43300000, len: 0x100000,
comment: "edma Memory (1 MB)"
};
var evmDRA7XX_EDMA_TC0 = {
name: "EDMATC0", space: "data", access: "RWX",
base: 0x43400000, len: 0x100000,
comment: "edma tc0 Memory (1 MB)"
};
var evmDRA7XX_EDMA_TC1 = {
name: "EDMATC1", space: "data", access: "RWX",
base: 0x43500000, len: 0x100000,
comment: "edma tc1 Memory (1 MB)"
};
var evmDRA7XX_MCASP1 = {
name: "DSPMCASP1", space: "data", access: "RWX",
base: 0x45800000, len: 0x100000,
comment: "MCASP1 Memory (1 MB)"
};
var evmDRA7XX_MCASP2 = {
name: "DSPMCASP2", space: "data", access: "RWX",
base: 0x45C00000, len: 0x100000,
comment: "MCASP2 Memory (1 MB)"
};
var evmDRA7XX_MCASP3 = {
name: "DSPMCASP3", space: "data", access: "RWX",
base: 0x46000000, len: 0x100000,
comment: "MCASP3 Memory (1 MB)"
};
var evmDRA7XX_DSPEDMA_TC0 = {
name: "DSPEDMATC0", space: "data", access: "RWX",
base: 0x40D05000, len: 0x1000,
comment: "dsp edma tc0 Memory (4 KB)"
};
var evmDRA7XX_DSPEDMA_TC1 = {
name: "DSPEDMATC1", space: "data", access: "RWX",
base: 0x40D06000, len: 0x1000,
comment: "dsp edma tc1 Memory (4 KB)"
};
var evmDRA7XX_DSPEDMA_CC = {
name: "DSPEDMACC", space: "data", access: "RWX",
base: 0x40D10000, len: 0x8000,
comment: "dsp edma cc Memory (32 KB)"
};
var evmDRA7XX_MAP_MEM001 = {
name: "MAP_MEM001", space: "data", access: "RWX",
base: 0x95400000, len: 0x1000,
comment: "MAP_MEM001 Memory (4 KB)"
};
var evmDRA7XX_MAP_MEM002 = {
name: "MAP_MEM002", space: "data", access: "RWX",
base: 0x95401000, len: 0x1000,
comment: "MAP_MEM003 Memory (4 KB)"
};
var evmDRA7XX_MAP_MEM003 = {
name: "MAP_MEM003", space: "data", access: "RWX",
base: 0x95402000, len: 0x1000,
comment: "MAP_MEM003 Memory (4 KB)"
};
var evmDRA7XX_MAP_MEM004 = {
name: "MAP_MEM004", space: "data", access: "RWX",
base: 0x95403000, len: 0x1000,
comment: "MAP_MEM004 Memory (4 KB)"
};
var evmDRA7XX_MAP_MEM005 = {
name: "MAP_MEM005", space: "data", access: "RWX",
base: 0x95404000, len: 0x1000,
comment: "MAP_MEM005 Memory (4 KB)"
};
var evmDRA7XX_MAP_MEM006 = {
name: "MAP_MEM006", space: "data", access: "RWX",
base: 0x95405000, len: 0x1000,
comment: "MAP_MEM006 Memory (4 KB)"
};
var evmDRA7XX_MAP_MEM007 = {
name: "MAP_MEM007", space: "data", access: "RWX",
base: 0x95406000, len: 0x1000,
comment: "MAP_MEM007 Memory (4 KB)"
};
var evmDRA7XX_MAP_MEM008 = {
name: "MAP_MEM008", space: "data", access: "RWX",
base: 0x95407000, len: 0x1000,
comment: "MAP_MEM008 Memory (4 KB)"
};
/* Shared region definition used in GateMP app */
var evmDRA7XX_SR_0 = {
name: "SR_0", space: "data", access: "RWX",
base: 0x95400000, len: 0x100000,
comment: "SR#0 Memory (1 MB)"
};
/* Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
*
* --- External Memory ---
* Virtual Physical Size Comment
* ------------------------------------------------------------------------
* 9500_4000 ????_???? 10_0000 ( ~1 MB) EXT_CODE
* 9510_0000 ????_???? 10_0000 ( 1 MB) EXT_DATA
* 9520_0000 ????_???? 30_0000 ( 3 MB) EXT_HEAP
* 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF
* 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA
* 9F07_0000 9F07_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
*/
var evmDRA7XX_ExtMemMapDsp = {
EXT_CODE: {
name: "EXT_CODE",
base: 0x95000000,
len: 0x00100000,
space: "code",
access: "RWX"
},
EXT_DATA: {
name: "EXT_DATA",
base: 0x95100000,
len: 0x00100000,
space: "data",
access: "RW"
},
EXT_HEAP: {
name: "EXT_HEAP",
base: 0x95200000,
len: 0x00200000,
space: "data",
access: "RW"
},
TRACE_BUF: {
name: "TRACE_BUF",
base: 0x9F000000,
len: 0x00060000,
space: "data",
access: "RW"
},
EXC_DATA: {
name: "EXC_DATA",
base: 0x9F060000,
len: 0x00010000,
space: "data",
access: "RW"
},
PM_DATA: {
name: "PM_DATA",
base: 0x9F070000,
len: 0x00020000,
space: "data",
access: "RWX" /* should this have execute perm? */
},
EDMA: {
name: evmDRA7XX_EDMA.name,
base: evmDRA7XX_EDMA.base,
len: evmDRA7XX_EDMA.len,
space: "data",
access: "RW"
},
EDMATC0: {
name: evmDRA7XX_EDMA_TC0.name,
base: evmDRA7XX_EDMA_TC0.base,
len: evmDRA7XX_EDMA_TC0.len,
space: "data",
access: "RW"
},
EDMATC1: {
name: evmDRA7XX_EDMA_TC1.name,
base: evmDRA7XX_EDMA_TC1.base,
len: evmDRA7XX_EDMA_TC1.len,
space: "data",
access: "RW"
},
DSP_MCASP1: {
name: evmDRA7XX_MCASP1.name,
base: evmDRA7XX_MCASP1.base,
len: evmDRA7XX_MCASP1.len,
space: "data",
access: "RW"
},
DSP_MCASP2: {
name: evmDRA7XX_MCASP2.name,
base: evmDRA7XX_MCASP2.base,
len: evmDRA7XX_MCASP2.len,
space: "data",
access: "RW"
},
DSP_MCASP3: {
name: evmDRA7XX_MCASP3.name,
base: evmDRA7XX_MCASP3.base,
len: evmDRA7XX_MCASP3.len,
space: "data",
access: "RW"
},
DSP_EDMATC0: {
name: evmDRA7XX_DSPEDMA_TC0.name,
base: evmDRA7XX_DSPEDMA_TC0.base,
len: evmDRA7XX_DSPEDMA_TC0.len,
space: "data",
access: "RW"
},
DSP_EDMATC1: {
name: evmDRA7XX_DSPEDMA_TC1.name,
base: evmDRA7XX_DSPEDMA_TC1.base,
len: evmDRA7XX_DSPEDMA_TC1.len,
space: "data",
access: "RW"
},
DSP_EDMACC: {
name: evmDRA7XX_DSPEDMA_CC.name,
base: evmDRA7XX_DSPEDMA_CC.base,
len: evmDRA7XX_DSPEDMA_CC.len,
space: "data",
access: "RW"
},
};
Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
externalMemoryMap: [
[ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
[ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
[ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
[ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
[ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
[ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ],
[ evmDRA7XX_EDMA.name, evmDRA7XX_ExtMemMapDsp.EDMA ],
[ evmDRA7XX_EDMA_TC0.name, evmDRA7XX_ExtMemMapDsp.EDMATC0 ],
[ evmDRA7XX_EDMA_TC1.name, evmDRA7XX_ExtMemMapDsp.EDMATC1 ],
[ evmDRA7XX_MCASP1.name, evmDRA7XX_ExtMemMapDsp.DSP_MCASP1 ],
[ evmDRA7XX_MCASP2.name, evmDRA7XX_ExtMemMapDsp.DSP_MCASP2 ],
[ evmDRA7XX_MCASP3.name, evmDRA7XX_ExtMemMapDsp.DSP_MCASP3 ],
[ evmDRA7XX_DSPEDMA_TC0.name, evmDRA7XX_ExtMemMapDsp.DSP_EDMATC0 ],
[ evmDRA7XX_DSPEDMA_TC1.name, evmDRA7XX_ExtMemMapDsp.DSP_EDMATC1 ],
[ evmDRA7XX_DSPEDMA_CC.name, evmDRA7XX_ExtMemMapDsp.DSP_EDMACC ],
],
codeMemory: "EXT_CODE",
dataMemory: "EXT_DATA",
stackMemory: "EXT_DATA",
};
Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] =
Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];
/* Memory Map for ti.platforms.evmDRA7XX:ipu2
*
* --- External Memory ---
* Virtual Physical Size Comment
* ------------------------------------------------------------------------
* 0000_4000 ????_???? 5F_C000 ( ~6 MB) EXT_CODE
* 8000_0000 ????_???? 60_0000 ( 6 MB) EXT_DATA
* 8060_0000 ????_???? 960_0000 ( 86 MB) EXT_HEAP
* 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF
* 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA
* 9F07_0000 9F07_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
*/
var evmDRA7XX_ExtMemMapIpu2 = {
EXT_CODE: {
name: "EXT_CODE",
base: 0x00004000,
len: 0x005FC000,
space: "code",
access: "RWX"
},
EXT_DATA: {
name: "EXT_DATA",
base: 0x80000000,
len: 0x00600000,
space: "data",
access: "RW"
},
EXT_HEAP: {
name: "EXT_HEAP",
base: 0x80600000,
len: 0x09600000,
space: "data",
access: "RW"
},
TRACE_BUF: {
name: "TRACE_BUF",
base: 0x9F000000,
len: 0x00060000,
space: "data",
access: "RW"
},
EXC_DATA: {
name: "EXC_DATA",
base: 0x9F060000,
len: 0x00010000,
space: "data",
access: "RW"
},
PM_DATA: {
name: "PM_DATA",
base: 0x9F070000,
len: 0x00020000,
space: "data",
access: "RWX" /* should this have execute perm? */
}
};
Build.platformTable["ti.platforms.evmDRA7XX:ipu2"] = {
externalMemoryMap: [
[ "EXT_CODE", evmDRA7XX_ExtMemMapIpu2.EXT_CODE ],
[ "EXT_DATA", evmDRA7XX_ExtMemMapIpu2.EXT_DATA ],
[ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu2.EXT_HEAP ],
[ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu2.TRACE_BUF ],
[ "EXC_DATA", evmDRA7XX_ExtMemMapIpu2.EXC_DATA ],
[ "PM_DATA", evmDRA7XX_ExtMemMapIpu2.PM_DATA ]
],
codeMemory: "EXT_CODE",
dataMemory: "EXT_DATA",
stackMemory: "EXT_DATA",
};
/* Memory Map for ti.platforms.evmDRA7XX:ipu1
*
* --- External Memory ---
* Virtual Physical Size Comment
* ------------------------------------------------------------------------
* 0000_4000 ????_???? F_C000 ( ~1 MB) EXT_CODE
* 8000_0000 ????_???? 20_0000 ( 2 MB) EXT_DATA
* 8020_0000 ????_???? 30_0000 ( 3 MB) EXT_HEAP
* 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF
* 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA
* 9F07_0000 9F07_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
*/
var evmDRA7XX_ExtMemMapIpu1 = {
EXT_CODE: {
name: "EXT_CODE",
base: 0x00004000,
len: 0x000FC000,
space: "code",
access: "RWX"
},
EXT_DATA: {
name: "EXT_DATA",
base: 0x80000000,
len: 0x00200000,
space: "data",
access: "RW"
},
EXT_HEAP: {
name: "EXT_HEAP",
base: 0x80200000,
len: 0x00300000,
space: "data",
access: "RW"
},
TRACE_BUF: {
name: "TRACE_BUF",
base: 0x9F000000,
len: 0x00060000,
space: "data",
access: "RW"
},
EXC_DATA: {
name: "EXC_DATA",
base: 0x9F060000,
len: 0x00010000,
space: "data",
access: "RW"
},
PM_DATA: {
name: "PM_DATA",
base: 0x9F070000,
len: 0x00020000,
space: "data",
access: "RWX" /* should this have execute perm? */
}
};
Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
externalMemoryMap: [
[ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
[ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
[ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
[ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
[ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
[ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ]
],
codeMemory: "EXT_CODE",
dataMemory: "EXT_DATA",
stackMemory: "EXT_DATA",
};
9、资源表文件：
/*
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== rsc_table_dsp.h ========
*
* Define the resource table entries for all DSP cores. This will be
* incorporated into corresponding base images, and used by the remoteproc
* on the host-side to allocated/reserve resources.
*
*/
#ifndef _RSC_TABLE_DSP_H_
#define _RSC_TABLE_DSP_H_
#include <ti/ipc/remoteproc/rsc_types.h>
/* DSP Memory Map */
#define L4_DRA7XX_BASE 0x4A000000
#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG 0x4A000000
#define L4_PERIPHERAL_L4PER1 0x48000000
#define DSP_PERIPHERAL_L4PER1 0x48000000
#define L4_PERIPHERAL_L4PER2 0x48400000
#define DSP_PERIPHERAL_L4PER2 0x48400000
#define L4_PERIPHERAL_L4PER3 0x48800000
#define DSP_PERIPHERAL_L4PER3 0x48800000
#define L4_PERIPHERAL_L4EMU 0x54000000
#define DSP_PERIPHERAL_L4EMU 0x54000000
#define L3_PERIPHERAL_DMM 0x4E000000
#define DSP_PERIPHERAL_DMM 0x4E000000
#define L3_TILER_MODE_0_1 0x60000000
#define DSP_TILER_MODE_0_1 0x60000000
#define L3_TILER_MODE_2 0x70000000
#define DSP_TILER_MODE_2 0x70000000
#define L3_TILER_MODE_3 0x78000000
#define DSP_TILER_MODE_3 0x78000000
#define L3_PERIPHERAL_EDMA_TPCC 0x43300000
#define DSP_PERIPHERAL_EDMA_TPCC 0x43300000
#define DSP_PERIPHERAL_EDMA_SIZE (SZ_1M*1)
#define L3_PERIPHERAL_EDMA_TC0 0x43400000
#define DSP_PERIPHERAL_EDMA_TC0 0x43400000
#define L3_PERIPHERAL_EDMA_TC1 0x43500000
#define DSP_PERIPHERAL_EDMA_TC1 0x43500000
#define L3_PERIPHERAL_DSP_EDMA_TC0 0x40D05000
#define DSP_PERIPHERAL_DSP_EDMA_TC0 0x40D05000
#define L3_PERIPHERAL_DSP_EDMA_TC1 0x40D06000
#define DSP_PERIPHERAL_DSP_EDMA_TC1 0x40D06000
#define L3_PERIPHERAL_DSP_EDMA_CC 0x40D10000
#define DSP_PERIPHERAL_DSP_EDMA_CC 0x40D10000
#define L3_PERIPHERAL_MCASP1 0x45800000
#define DSP_PERIPHERAL_MCASP1 0x45800000
#define L3_PERIPHERAL_MCASP2 0x45C00000
#define DSP_PERIPHERAL_MCASP2 0x45C00000
#define L3_PERIPHERAL_MCASP3 0x46000000
#define DSP_PERIPHERAL_MCASP3 0x46000000
//#define L3_PERIPHERAL_MCSPI1TP 0x48098000
//#define DSP_PERIPHERAL_MCSPI1TP 0x48098000
//
//#define L3_PERIPHERAL_MCSPI1TA 0x48099000
//#define DSP_PERIPHERAL_MCSPI1TA 0x48099000
#define DSP_PERIPHERAL_MCASP_SIZE (SZ_1M*1)
#define DSP_MEM_TEXT 0x95000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS 0x80000000
#define DSP_MEM_DATA 0x95100000
#define DSP_MEM_HEAP 0x95200000
#define DSP_MEM_IPC_DATA 0x9F000000
#define DSP_MEM_IPC_VRING 0x99000000
#define DSP_MEM_RPMSG_VRING0 0x99000000
#define DSP_MEM_RPMSG_VRING1 0x99004000
#define DSP_MEM_VRING_BUFS0 0x99040000
#define DSP_MEM_VRING_BUFS1 0x99080000
#define DSP_MEM_IPC_VRING_SIZE SZ_1M
#define DSP_MEM_IPC_DATA_SIZE SZ_1M
#define DSP_MEM_TEXT_SIZE SZ_1M
#define DSP_MEM_DATA_SIZE SZ_1M
#define DSP_MEM_HEAP_SIZE (SZ_1M * 2)
#define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
/* NOTE: Make sure this matches what is configured in the linux device tree */
#define DSP_CMEM_IOBUFS 0xA0000000
#define PHYS_CMEM_IOBUFS 0xA0000000
#define DSP_CMEM_IOBUFS_SIZE (SZ_1M * 192)
#define L2_RAM_BASE 0x40808000
#define DSP_L2_RAM_BASE 0x40808000
#define DSP_L2_RAM_SIZE 0x40000
/*
* Assign fixed RAM addresses to facilitate a fixed MMU table.
*/
#define VAYU_DSP_1
/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#if defined (VAYU_DSP_1)
#define PHYS_MEM_IPC_VRING 0x99000000
#elif defined (VAYU_DSP_2)
#define PHYS_MEM_IPC_VRING 0x9F000000
#endif
/* Need to be identical to that of IPU */
#define PHYS_MEM_IOBUFS 0xBA300000
/*
* Sizes of the virtqueues (expressed in number of buffers supported,
* and must be power of 2)
*/
#define DSP_RPMSG_VQ0_SIZE 256
#define DSP_RPMSG_VQ1_SIZE 256
/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES 1
struct my_resource_table {
struct resource_table base;
UInt32 offset[27]; /* Should match 'num' in actual definition */
/* rpmsg vdev entry */
struct fw_rsc_vdev rpmsg_vdev;
struct fw_rsc_vdev_vring rpmsg_vring0;
struct fw_rsc_vdev_vring rpmsg_vring1;
/* text carveout entry */
struct fw_rsc_carveout text_cout;
/* data carveout entry */
struct fw_rsc_carveout data_cout;
/* heap carveout entry */
struct fw_rsc_carveout heap_cout;
/* ipcdata carveout entry */
struct fw_rsc_carveout ipcdata_cout;
/* trace entry */
struct fw_rsc_trace trace;
/* devmem entry */
struct fw_rsc_devmem devmem0;
/* devmem entry */
struct fw_rsc_devmem devmem1;
/* devmem entry */
struct fw_rsc_devmem devmem2;
/* devmem entry */
struct fw_rsc_devmem devmem3;
/* devmem entry */
struct fw_rsc_devmem devmem4;
/* devmem entry */
struct fw_rsc_devmem devmem5;
/* devmem entry */
struct fw_rsc_devmem devmem6;
/* devmem entry */
struct fw_rsc_devmem devmem7;
/* devmem entry */
struct fw_rsc_devmem devmem8;
/* devmem entry */
struct fw_rsc_devmem devmem9;
/* devmem entry */
struct fw_rsc_devmem devmem10;
/* devmem entry */
struct fw_rsc_devmem devmem11;
/* devmem entry */
struct fw_rsc_devmem devmem12;
/* devmem entry */
struct fw_rsc_devmem devmem13;
/* devmem entry */
struct fw_rsc_devmem devmem14;
/* devmem entry */
struct fw_rsc_devmem devmem15;
/* devmem entry */
struct fw_rsc_devmem devmem16;
/* devmem entry */
struct fw_rsc_devmem devmem17;
/* devmem entry */
struct fw_rsc_devmem devmem18;
/* devmem entry */
struct fw_rsc_devmem devmem19;
/* devmem entry */
struct fw_rsc_devmem devmem20;
};
extern char ti_trace_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
1, /* we're the first version that implements this */
27, /* number of entries in the table */
0, 0, /* reserved, must be zero */
/* offsets to entries */
{
offsetof(struct my_resource_table, rpmsg_vdev),
offsetof(struct my_resource_table, text_cout),
offsetof(struct my_resource_table, data_cout),
offsetof(struct my_resource_table, heap_cout),
offsetof(struct my_resource_table, ipcdata_cout),
offsetof(struct my_resource_table, trace),
offsetof(struct my_resource_table, devmem0),
offsetof(struct my_resource_table, devmem1),
offsetof(struct my_resource_table, devmem2),
offsetof(struct my_resource_table, devmem3),
offsetof(struct my_resource_table, devmem4),
offsetof(struct my_resource_table, devmem5),
offsetof(struct my_resource_table, devmem6),
offsetof(struct my_resource_table, devmem7),
offsetof(struct my_resource_table, devmem8),
offsetof(struct my_resource_table, devmem9),
offsetof(struct my_resource_table, devmem10),
offsetof(struct my_resource_table, devmem11),
offsetof(struct my_resource_table, devmem12),
offsetof(struct my_resource_table, devmem13),
offsetof(struct my_resource_table, devmem14),
offsetof(struct my_resource_table, devmem15),
offsetof(struct my_resource_table, devmem16),
offsetof(struct my_resource_table, devmem17),
offsetof(struct my_resource_table, devmem18),
offsetof(struct my_resource_table, devmem19),
offsetof(struct my_resource_table, devmem20),
},
/* rpmsg vdev entry */
{
TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
/* no config data */
},
/* the two vrings */
{ DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
{ DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
{
TYPE_CARVEOUT,
DSP_MEM_TEXT, 0,
DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
},
{
TYPE_CARVEOUT,
DSP_MEM_DATA, 0,
DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
},
{
TYPE_CARVEOUT,
DSP_MEM_HEAP, 0,
DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
},
{
TYPE_CARVEOUT,
DSP_MEM_IPC_DATA, 0,
DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
},
{
TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
},
{
TYPE_DEVMEM,
DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
},
{
TYPE_DEVMEM,
DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
},
{
TYPE_DEVMEM,
DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
},
{
TYPE_DEVMEM,
DSP_TILER_MODE_2, L3_TILER_MODE_2,
SZ_128M, 0, 0, "DSP_TILER_MODE_2",
},
{
TYPE_DEVMEM,
DSP_TILER_MODE_3, L3_TILER_MODE_3,
SZ_128M, 0, 0, "DSP_TILER_MODE_3",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
},
{
TYPE_DEVMEM,
DSP_CMEM_IOBUFS, PHYS_CMEM_IOBUFS,
DSP_CMEM_IOBUFS_SIZE, 0, 0, "DSP_CMEM_IOBUFS",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_EDMA_TPCC, L3_PERIPHERAL_EDMA_TPCC,
DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_PERIPHERAL_EDMA_TPCC",
},
{
TYPE_DEVMEM,
L3_PERIPHERAL_MCASP1, L3_PERIPHERAL_MCASP1,
DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_MCASP1",
},
{
TYPE_DEVMEM,
L3_PERIPHERAL_MCASP2, L3_PERIPHERAL_MCASP2,
DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_MCASP2",
},
{
TYPE_DEVMEM,
L3_PERIPHERAL_MCASP3, L3_PERIPHERAL_MCASP3,
DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_MCASP3",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_EDMA_TC0, L3_PERIPHERAL_EDMA_TC0,
DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_PERIPHERAL_EDMA_TC0",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_EDMA_TC1, L3_PERIPHERAL_EDMA_TC1,
DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_PERIPHERAL_EDMA_TC1",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_DSP_EDMA_TC0, L3_PERIPHERAL_DSP_EDMA_TC0,
0x1000, 0, 0, "L3_PERIPHERAL_DSP_EDMA_TC0",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_DSP_EDMA_TC1, L3_PERIPHERAL_DSP_EDMA_TC1,
0x1000, 0, 0, "L3_PERIPHERAL_DSP_EDMA_TC1",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_DSP_EDMA_CC, L3_PERIPHERAL_DSP_EDMA_CC,
0x8000, 0, 0, "L3_PERIPHERAL_DSP_EDMA_CC",
},
};
#endif /* _RSC_TABLE_DSP_H_ */
问题：为什么DSP核的定时器会不精确？或者说如何使中断中程序每次运行的时间一致（高电平持续长度无波动）？
