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DRA821U: 2G中的PORT1不能正常的发送报文,超出配置的发送buffer个数后,请求无空闲buffer,导致发送失败。

Part Number: DRA821U


Hi  @Zhang, Semon

在使用821 MCU域中的2G CPSW中的Port2作为以太网实体时和5G中的一个port互联,在macl中配置发送和接收的buffer个数为48。初始化成功后,2G侧PORT1发送报文,发送超过配置的buffer后,不能再发送数据,请求不到空闲的buffer,能正常的接收报文。数组gEthTxCqRingMem不能写入数据。

uint8 ArpData_VLAN3[32] =
{
  0x00,0x03,0x08,06,0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x00, 0x03, 0x19, 0x00, 0x00, 0x01,
  0xa9, 0xfe, 0xfe, 0xab, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0xfe, 0xab, 0xa8
};
uint8 MacDestUncastAddress[8] = {0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x06};
uint8 *TmpBuffPtr;

void Tx_EthFrame_VLAN3(void)
{
	boolean Txstatus=0; 
	uint16 Tmp_Txlenghth1 = 32;

    
	Global_TempUSage[1] = Eth_ProvideTxBuffer(0, 0, &TmpBuffIdx, &TmpBuffPtr, &Tmp_Txlenghth1);

	ArpData[15] = gCnt++;

    if(TmpBuffPtr != NULL_PTR)
    {
        TxBufferFill(TmpBuffPtr, Tmp_Txlenghth1, ArpData_VLAN3);
        
        EthDemoRetVal[1] = Eth_Transmit(0, TmpBuffIdx, ETH_VLAN_PROTOCOL, Txstatus, Tmp_Txlenghth1, &MacDestUncastAddress[0]);
    }
    else
        EthDemoRetVal[1] = 1;

}

#ifdef __cplusplus
extern "C" {
#endif

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
/**
*  \brief ETH Build Variant
*   STD_ON for VariantPreCompile / STD_OFF for VariantPostBuild
*/
#define ETH_PRE_COMPILE_VARIANT                    (STD_ON)
/** \brief Enable/disable SPI get version info API */
#define ETH_VERSION_INFO_API                       (STD_ON)
/** \brief Enable/disable Eth time sync related API  */
#define ETH_GLOBALTIMESUPPORT_API                  (STD_OFF)
/** \brief Enable/Disable Development Error Detection */
#define ETH_DEV_ERROR_DETECT                       (STD_OFF)
/** \brief Enable/disable Eth get counter values API  */
#define ETH_GET_COUNTER_VALUES_API                 (STD_ON)
/** \brief Enable/disable Eth get RX stats count API  */
#define ETH_GET_RX_STATS_API                       (STD_ON)
/** \brief Enable/disable Eth get TX stats count API  */
#define ETH_GET_TX_STATS_API                       (STD_ON)
/** \brief Enable/disable Eth get TX error stats count API  */
#define ETH_GET_TX_ERROR_COUNTERSVALUES_API        (STD_ON)
/** \brief Enable/disable Eth zero-copy transmit API */
#define ETH_ZERO_COPY_TX                           (STD_OFF)
/** \brief Enable/disable Eth queue-based APIs */
#define ETH_USE_Q_APIS                             (STD_OFF)

/** \brief Enable/disable Eth MII related API  */
#define ETH_ENABLE_MII_API                         (STD_ON)
/** \brief Enable/disable optional API Eth_UpdatePhysAddrFilter */
#define ETH_UPDATE_PHYS_ADDR_FILTER_API            (STD_ON)
/** \brief Enable/disable optional API Eth_NotifyVirtmacMsgReceived */
#define ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API       (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacSubscribeAllTraffic */
#define ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API     (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacUnsubscribeAllTraffic */
#define ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API   (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacSubscribeDstMac */
#define ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API         (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacUnsubscribeDstMac */
#define ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API       (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacAssociateIPv4Macaddr */
#define ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API    (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacDisassociateIPv4Macaddr */
#define ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacAddUnicastAddr */
#define ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API     (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacAddMcastAddr */
#define ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API       (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacDelAddr */
#define ETH_VIRTUALMAC_DEL_MACADDR_API             (STD_OFF)
/** \brief Enable/disable optional API Eth_SendCustomNotify */
#define ETH_VIRTUALMAC_SEND_CUSTOM_NOTIFY_API      (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacAddVlan */
#define ETH_VIRTUALMAC_ADD_VLAN_API                (STD_OFF)
/** \brief Enable/disable optional API Eth_DispatchVirtmacDelVlan */
#define ETH_VIRTUALMAC_DEL_VLAN_API                (STD_OFF)

/** \brief Enable/disable transmit interrupt */
#define ETH_ENABLE_TX_INTERRUPT        (STD_ON)
/** \brief Enable/disable receive interrupt */
#define ETH_ENABLE_RX_INTERRUPT        (STD_ON)
/** \brief Number of TX buffers */
#define ETH_NUM_TX_BUFFERS             (48U)
/** \brief Number of RX buffers */
#define ETH_NUM_RX_BUFFERS             (48U)
/** \brief Limits the maximum transmit buffer length (frame length) in bytes */
#define ETH_TX_BUF_LEN_BYTE            (1522U)
/** \brief Limits the maximum receive buffer length (frame length) in bytes */
#define ETH_RX_BUF_LEN_BYTE            (1522U)

/** \brief Enable/Disable DMA descriptors in cached memory */
#define ETH_DESC_IN_CACHED_MEMORY      (STD_ON)
/** \brief Enable/Disable DMA rings in cached memory */
#define ETH_RING_IN_CACHED_MEMORY      (STD_ON)



/** \brief ISR type */
#define ETH_ISR_TYPE                   (ETH_ISR_CAT2)
/** \name Pre-compile switches for MAC addr configuration, ALE conf. etc. */
#define ETH_USE_DEFAULT_MAC_ADDR       (STD_OFF)
/** \brief Counter ID for counter used to count wait ticks */
#define ETH_OS_COUNTER_ID              ((CounterType)OsCounter_Core0)
/** \brief Timeout value for a wait (busy wait) */
#define ETH_TIMEOUT_DURATION           (3200U)

/** \brief MAC address of the controller in network byte order */
#define ETH_CTRL_PHY_ADDRESS           { 0xaaU,0xbbU,0xccU,0xddU,0xeeU,0x07U,}

/** \brief Enable/disable Virtual MAC support for CPSW9G */
#define ETH_VIRTUALMAC_SUPPORT        (STD_OFF)

/** \brief Timeout value for Firmware Attach msg received from server
  *  Units of timeout is in terms of number of invocations of Eth_MainFunction
  */
#define ETH_VIRTUALMAC_FWINFO_TIMEOUT (10U)

/* ========================================================================== */
/*                          External Function Prototype                       */
/* ========================================================================== */
/** \brief Function to write-back and invalidate cache */
extern void EthApp_wbInvCache(uint8 *buf, uint16 len);
/** \brief Function to write-back cache */
extern void EthApp_wbCache(uint8 *buf, uint16 len);
/** \brief Function to invalidate cache */
extern void EthApp_invCache(uint8 *buf, uint16 len);

/**
 *  \name ETH DEM Error codes to report
 *
 *  Pre-compile switches for enabling/disabling DEM events
 *  @{
 */
#define DemConf_DemEventParameter_ETH_DEM_NO_EVENT (0xFFFFU)
#define ETH_DEM_NO_EVENT DemConf_DemEventParameter_ETH_DEM_NO_EVENT

#ifndef ETH_E_HARDWARE_ERROR
/** \brief Hardware failed */
#define ETH_E_HARDWARE_ERROR       (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_LATECOLLISION
/** \brief Late collision */
#define ETH_E_LATECOLLISION        (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_MULTIPLECOLLISION
/** \brief Multiple collision */
#define ETH_E_MULTIPLECOLLISION    (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_SINGLECOLLISION
/** \brief Single collision */
#define ETH_E_SINGLECOLLISION      (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_ALIGNMENT
/** \brief Alignment error */
#define ETH_E_ALIGNMENT            (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_OVERSIZEFRAME
/** \brief Oversize Frame */
#define ETH_E_OVERSIZEFRAME        (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_UNDERSIZEFRAME
/** \brief Undersize frame */
#define ETH_E_UNDERSIZEFRAME       (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_CRC
/** \brief CRC Error */
#define ETH_E_CRC                  (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_RX_FRAMES_LOST
/** \brief Received Frames lost */
#define ETH_E_RX_FRAMES_LOST       (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_ACCESS
/** \brief Hardware failed */
#define ETH_E_ACCESS               (ETH_DEM_NO_EVENT)
#endif

#ifndef ETH_E_TX_INTERNAL
/** \brief TX packet descriptor returned by UDMA is corrupted.
 *         Invalid data pointer in descriptor
 */
#define ETH_E_TX_INTERNAL          (ETH_DEM_NO_EVENT)
#endif

/* @} */

/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */

/* ========================================================================== */
/*                         Generate Configuration                             */
/* ========================================================================== */
/**< \brief Pointer to the generated configuration */
extern const struct Eth_ConfigType_s EthConfig_MCU_PC;

/**< \brief Configuration of the driver */
#define ETH_DRV_CONFIG_0    ((const Eth_ConfigType *) &EthConfig_MCU_PC)

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

/* None */

#ifdef __cplusplus
}
#endif
/**< \brief Ethernet configurations
        Generated, not expected be modified manually */
ETH_CONFIG_DATA_SECTION CONST(Eth_ConfigType, ETH_CONFIG_DATA)
    EthConfig_MCU_PC =
{
    .ctrlIdx = ETH_CONTROLLER_ID_0,
    /**< Controller index, 0 always */
    .udmaInstId = UDMA_INST_ID_MCU_0,
    /**< Instance of UDMA to be used */
    .dmaTxChIntrNum     =    80U,
    /**< DMA TX channel interrupt number */
    .dmaRxChIntrNum     =    81U,
    /**< DMA RX channel interrupt number */
    .mdioBusFreq        =    2200000U,
    /**< MDIO bus clock (MDCLK) frequency (in Hz) */
    .connType           =    ETH_MAC_CONN_TYPE_RMII_100,
    /**< MII connection type */
    .loopback           =    false,
    /**< Loopback enable */
    .enableCacheOps     =     (uint32)TRUE,
    /**< Packet memory is cacheable */
    .cacheWbInv         =     (Eth_CacheWbInv) &EthApp_wbInvCache,
    /**< Cache write-back invalidate function */
    .cacheWb            =     (Eth_CacheWb) &EthApp_wbCache,
    /**< Cache write-back function */
    .cacheInv           =     (Eth_CacheInv) &EthApp_invCache,
    /**< Cache invalidate function */
    .enetType           =     ETH_ENETTYPE_CPSW2G,
    /**< CPSW type */
    .macPort            =     ETH_PORT_MAC_PORT_1,
    /**< Port mode */
    .enableVirtualMac   =     FALSE,
    /**< Virtual MAC mode */
};
#define  ETH_STOP_SEC_CONFIG_DATA
#include "Eth_MemMap.h"

  • Eth_Init(NULL_PTR);
    Eth_SetControllerMode(0, ETH_MODE_ACTIVE);
    BufReq_ReturnType Global_TempUSage;
    Eth_BufIdxType TmpBuffIdx;
    Std_ReturnType EthDemoRetVal;
    uint8 ArpData_VLAN3[32] =
    {
      0x00,0x03,0x08,06,0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x00, 0x03, 0x19, 0x00, 0x00, 0x01,
      0xa9, 0xfe, 0xfe, 0xab, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa9, 0xfe, 0xab, 0xa8
    };
    uint8 MacDestBrodaddress[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
    uint8 MacDestUncastAddress[8] = {0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x06};
    uint8 *TmpBuffPtr;
    void Tx_EthFrame_VLAN3(void)
    {
    	boolean Txstatus=0; 
    	uint16 Tmp_Txlenghth1 = 32;
    
        
    	Global_TempUSage[1] = Eth_ProvideTxBuffer(0, 0, &TmpBuffIdx, &TmpBuffPtr, &Tmp_Txlenghth1);
    
    
        if(TmpBuffPtr != NULL_PTR)
        {
            TxBufferFill(TmpBuffPtr, Tmp_Txlenghth1, ArpData_VLAN3);
            
            EthDemoRetVal[1] = Eth_Transmit(0, TmpBuffIdx, ETH_VLAN_PROTOCOL, Txstatus, Tmp_Txlenghth1, &MacDestUncastAddress[0]);
        }
    
    
    }
    

    测试发送的代码,需要在周期任务中挂载一下。

  • STACK_SIZE = 0x00004000;
    Mode_SYS_Stack_Size = 8192;
    Mode_EXE_Stack_Size = 1024;
    Mode_SVC_Stack_Size = 1024;
    Mode_IRQ_Stack_Size = 1024;
    Mode_FIQ_Stack_Size = 1024;
    OSEE_HEAP_SIZE = 8096;

    EXTERN(Memlay_PorstRam_pst)
    EXTERN(Memlay_ShareRam_pst)

    ENTRY(_start)
    MEMORY
    {
    ATCM (RWX) : ORIGIN = 0x00000000, LENGTH = 0x00007FFF
    BTCM (RWX) : ORIGIN = 0x41010000, LENGTH = 0x00007FFF
    SRAM (RWX) : ORIGIN = 0x41C02000, LENGTH = 0x41CBFFFF + 1 - 0x41C02000
    DDR (RWX) : ORIGIN = 0x80100000, LENGTH = 2M
    DDR_DS (RW) : ORIGIN = 0x80300000, LENGTH = 1M

    /* DDR for MCU2_1 for Linux resource table [ size 1024 B ] */
    DDR_IPC_RESOURCE_TABLE(RW) : ORIGIN = 0xA3300000, LENGTH = 0x400

    /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 8.00 MB ] */
    DDR_IPC_VRING_MEM(RW) : ORIGIN = 0xA4000000, LENGTH = 8M

    /* Dummy area for unspecified input sections. Size 0 */
    /* causes an linker error if there is an input section not considered in linker command file. */
    must_be_empty : ORIGIN = 0, LENGTH = 0
    }
    SECTIONS
    {
    /DISCARD/ : {
    *(.comment)
    *(.ARM.exidx*)
    *(.gnu.linkonce.armexidix.*.*)
    }

    .vectors : {
    . = ALIGN(64);
    osee_vector_start = .;
    KEEP(*(.vectors))
    . = ALIGN(0x80);
    osee_vector_end = . - 1;
    osee_vector_log2ceil_size = ((osee_vector_end - osee_vector_start) <= (1 << 5) ? 5 : (osee_vector_end - osee_vector_start) <= (1 << 6) ? 6 : (osee_vector_end - osee_vector_start) <= (1 << 7) ? 7 : (osee_vector_end - osee_vector_start) <= (1 << 8) ? 8 :(osee_vector_end - osee_vector_start) <= (1 << 9) ? 9 : (osee_vector_end - osee_vector_start) <= (1 << 10) ? 10 : (osee_vector_end - osee_vector_start) <= (1 << 11) ? 11 : (osee_vector_end - osee_vector_start) <= (1 << 12) ? 12 : (osee_vector_end - osee_vector_start) <= (1 << 13) ? 13 : (osee_vector_end - osee_vector_start) <= (1 << 14) ? 14 : (osee_vector_end - osee_vector_start) <= (1 << 15) ? 15 : (osee_vector_end - osee_vector_start) <= (1 << 16) ? 16 : (osee_vector_end - osee_vector_start) <= (1 << 17) ? 17 : (osee_vector_end - osee_vector_start) <= (1 << 18) ? 18 : (osee_vector_end - osee_vector_start) <= (1 << 19) ? 19 : (osee_vector_end - osee_vector_start) <= (1 << 20) ? 20 : (osee_vector_end - osee_vector_start) <= (1 << 21) ? 21 : (osee_vector_end - osee_vector_start) <= (1 << 22) ? 22 : (osee_vector_end - osee_vector_start) <= (1 << 23) ? 23 : (osee_vector_end - osee_vector_start) <= (1 << 24) ? 24 : (osee_vector_end - osee_vector_start) <= (1 << 25) ? 25 : (osee_vector_end - osee_vector_start) <= (1 << 26) ? 26 : (osee_vector_end - osee_vector_start) <= (1 << 27) ? 27 : (osee_vector_end - osee_vector_start) <= (1 << 28) ? 28 : (osee_vector_end - osee_vector_start) <= (1 << 29) ? 29 : (osee_vector_end - osee_vector_start) <= (1 << 30) ? 30 : (osee_vector_end - osee_vector_start) <= (1 << 31) ? 31 : -1);
    } > ATCM
    .kernel_bss_percpu (NOLOAD) : ALIGN(8) {
    *(osee_kernel_bss_percpu)
    } > BTCM
    .kernel_data_percpu : ALIGN(8) {
    *(osee_kernel_data_percpu)
    } > BTCM AT > SRAM

    .startup : {
    . = ALIGN(64);
    *(.startup)
    *(osee_boot_kernel_text)
    *(.startupCode)
    . = ALIGN(8);
    } > SRAM

    .rodata.ipc : {
    *(.rodata.CddIpcConfiguraions_PC)
    . = ALIGN(8);
    } > SRAM

    .bss.ipc_vring_mem (NOLOAD) :
    {
    *(.bss.ipc_vring_mem)
    . = ALIGN(8);
    } > DDR_IPC_VRING_MEM

    .resource_table :
    {
    __RESOURCE_TABLE = .;
    *(.resource_table)
    . = ALIGN(8);
    __RESOURCE_TABLE_END = . - 1;
    } > DDR_IPC_RESOURCE_TABLE

    kernel_code_start_align : {
    . = ALIGN(osee_kernel_code_size_to_align);
    osee_kernel_code_start = .;
    } > DDR
    .kernel_text : {
    *(.boot)
    *(.kernel_text)
    *(osee_kernel_text)
    *(.gnu.linkonce.t.*)
    *(.plt)
    *(.gnu_warning)
    *(.gcc_execpt_table)
    *(.glue_7)
    *(.glue_7t)
    *(.vfp11_veneer)
    *(.ARM.extab)
    *(.gnu.linkonce.armextab.*)
    } > DDR
    OsApplication_Core0_code_start_align : {
    osee_OsApplication_Core0_code_start = .;
    } > DDR
    .OsApplication_Core0_text : ALIGN(8) {
    *(osee_OsApplication_Core0_text)
    *(*_OsApplication_Core0_text)
    } > DDR
    OsApplication_Core0_code_stop_align : {
    osee_OsApplication_Core0_code_end = .;
    } > DDR
    .text_cpu0 : {
    *(osee_core0_text)
    *(*_core0_text.*)
    } > DDR
    .init : {
    KEEP (*(.init))
    } > DDR
    .fini : {
    KEEP (*(.fini))
    } > DDR
    .interp : {
    KEEP (*(.interp))
    } > DDR
    .note-ABI-tag : {
    KEEP (*(.note-ABI-tag))
    } > DDR
    .ctors : {
    __CTOR_LIST__ = .;
    ___CTORS_LIST___ = .;
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    __CTOR_END__ = .;
    ___CTORS_END___ = .;
    } > DDR
    .dtors : {
    __DTOR_LIST__ = .;
    ___DTORS_LIST___ = .;
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    __DTOR_END__ = .;
    ___DTORS_END___ = .;
    } > DDR
    .fixup : {
    *(.fixup)
    } > DDR
    .eh_frame : {
    *(.eh_frame)
    } > DDR
    .eh_framehdr : {
    *(.eh_framehdr)
    } > DDR
    .gcc_except_table : {
    *(.gcc_except_table)
    } > DDR
    kernel_code_stop_align : {
    osee_kernel_code_stop = .;
    osee_kernel_code_log2ceil_size = ((osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 5) ? 5 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 6) ? 6 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 7) ? 7 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 8) ? 8 :(osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 9) ? 9 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 10) ? 10 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 11) ? 11 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 12) ? 12 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 13) ? 13 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 14) ? 14 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 15) ? 15 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 16) ? 16 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 17) ? 17 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 18) ? 18 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 19) ? 19 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 20) ? 20 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 21) ? 21 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 22) ? 22 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 23) ? 23 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 24) ? 24 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 25) ? 25 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 26) ? 26 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 27) ? 27 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 28) ? 28 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 29) ? 29 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 30) ? 30 : (osee_kernel_code_stop - osee_kernel_code_start) <= (1 << 31) ? 31 : -1);
    osee_kernel_code_size_to_align = 1 << osee_kernel_code_log2ceil_size;
    . = ALIGN(osee_kernel_code_size_to_align);
    osee_kernel_code_end = .;
    } > DDR
    api_code_start_align : {
    . = ALIGN(osee_api_code_size_to_align);
    osee_api_code_start = .;
    } > DDR
    .api_text : {
    *(osee_api_text)
    *(*_api_text)
    } > DDR
    .text : {
    *(.text)
    *(.text.*)
    *(*_TEXT_SECTION)
    } > DDR
    api_code_stop_align : {
    osee_api_code_stop = .;
    osee_api_code_log2ceil_size = ((osee_api_code_stop - osee_api_code_start) <= (1 << 5) ? 5 : (osee_api_code_stop - osee_api_code_start) <= (1 << 6) ? 6 : (osee_api_code_stop - osee_api_code_start) <= (1 << 7) ? 7 : (osee_api_code_stop - osee_api_code_start) <= (1 << 8) ? 8 :(osee_api_code_stop - osee_api_code_start) <= (1 << 9) ? 9 : (osee_api_code_stop - osee_api_code_start) <= (1 << 10) ? 10 : (osee_api_code_stop - osee_api_code_start) <= (1 << 11) ? 11 : (osee_api_code_stop - osee_api_code_start) <= (1 << 12) ? 12 : (osee_api_code_stop - osee_api_code_start) <= (1 << 13) ? 13 : (osee_api_code_stop - osee_api_code_start) <= (1 << 14) ? 14 : (osee_api_code_stop - osee_api_code_start) <= (1 << 15) ? 15 : (osee_api_code_stop - osee_api_code_start) <= (1 << 16) ? 16 : (osee_api_code_stop - osee_api_code_start) <= (1 << 17) ? 17 : (osee_api_code_stop - osee_api_code_start) <= (1 << 18) ? 18 : (osee_api_code_stop - osee_api_code_start) <= (1 << 19) ? 19 : (osee_api_code_stop - osee_api_code_start) <= (1 << 20) ? 20 : (osee_api_code_stop - osee_api_code_start) <= (1 << 21) ? 21 : (osee_api_code_stop - osee_api_code_start) <= (1 << 22) ? 22 : (osee_api_code_stop - osee_api_code_start) <= (1 << 23) ? 23 : (osee_api_code_stop - osee_api_code_start) <= (1 << 24) ? 24 : (osee_api_code_stop - osee_api_code_start) <= (1 << 25) ? 25 : (osee_api_code_stop - osee_api_code_start) <= (1 << 26) ? 26 : (osee_api_code_stop - osee_api_code_start) <= (1 << 27) ? 27 : (osee_api_code_stop - osee_api_code_start) <= (1 << 28) ? 28 : (osee_api_code_stop - osee_api_code_start) <= (1 << 29) ? 29 : (osee_api_code_stop - osee_api_code_start) <= (1 << 30) ? 30 : (osee_api_code_stop - osee_api_code_start) <= (1 << 31) ? 31 : -1);
    osee_api_code_size_to_align = 1 << osee_api_code_log2ceil_size;
    . = ALIGN(osee_api_code_size_to_align);
    osee_api_code_end = .;
    } > DDR
    all_const_start_align : {
    . = ALIGN(osee_all_const_size_to_align);
    osee_all_const_start = .;
    } > DDR
    .rodata : ALIGN(4) {
    *(*_const)
    *(*api_const_64)
    *(*api_const_32)
    *(*api_const_ptr)
    *(*api_const_16)
    *(*api_const_8)
    *(*api_const_bool)
    *(*api_const_unspecified)
    *(*api_const)
    *(*_const_64)
    *(*_const_32)
    *(*_const_ptr)
    *(*_const_16)
    *(*_const_8)
    *(*_const_bool)
    *(*_const_unspecified)
    *(*_postbuildstruct)
    *(*_postbuildconfig)
    *(.rodata)
    *(.rodata.*)
    *(.rodata1)
    *(.rodata1.*)
    *(.gnu.linkonce.r.*)
    *(.const.devgroup.*)
    *(.boardcfg_data)
    *(*_CONFIG_SECTION)
    . = ALIGN(8) ;
    PROVIDE(__clear_table = .);
    LONG(0 + ADDR(.kernel_bss_global)); LONG(SIZEOF(.kernel_bss_global));
    LONG(0 + ADDR(.kernel_bss)); LONG(SIZEOF(.kernel_bss));
    LONG(0 + ADDR(.sbss)); LONG(SIZEOF(.sbss));
    LONG(0 + ADDR(.sbss2)); LONG(SIZEOF(.sbss2));
    LONG(0 + ADDR(.tbss)); LONG(SIZEOF(.tbss));
    LONG(0 + ADDR(.api_bss)); LONG(SIZEOF(.api_bss));
    LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss));
    LONG(0 + ADDR(.OsApplication_Core0_bss)); LONG(SIZEOF(.OsApplication_Core0_bss));
    LONG(0 + ADDR(.kernel_bss_cpu0)); LONG(SIZEOF(.kernel_bss_cpu0));
    LONG(0 + ADDR(.api_bss_cpu0)); LONG(SIZEOF(.api_bss_cpu0));
    LONG(-1); LONG(-1);
    PROVIDE(__copy_table = .) ;
    LONG(LOADADDR(.kernel_data_percpu)); LONG(ADDR(.kernel_data_percpu)); LONG(SIZEOF(.kernel_data_percpu));
    LONG(-1); LONG(-1); LONG(-1);
    . = ALIGN(8);
    } > DDR
    .stack_sizes : ALIGN(4) {
    osEE_unwind_start = .;
    KEEP (*(.stack_sizes))
    osEE_unwind_end = .;
    } > DDR
    all_const_stop_align : {
    osee_all_const_stop = .;
    osee_all_const_log2ceil_size = ((osee_all_const_stop - osee_all_const_start) <= (1 << 5) ? 5 : (osee_all_const_stop - osee_all_const_start) <= (1 << 6) ? 6 : (osee_all_const_stop - osee_all_const_start) <= (1 << 7) ? 7 : (osee_all_const_stop - osee_all_const_start) <= (1 << 8) ? 8 :(osee_all_const_stop - osee_all_const_start) <= (1 << 9) ? 9 : (osee_all_const_stop - osee_all_const_start) <= (1 << 10) ? 10 : (osee_all_const_stop - osee_all_const_start) <= (1 << 11) ? 11 : (osee_all_const_stop - osee_all_const_start) <= (1 << 12) ? 12 : (osee_all_const_stop - osee_all_const_start) <= (1 << 13) ? 13 : (osee_all_const_stop - osee_all_const_start) <= (1 << 14) ? 14 : (osee_all_const_stop - osee_all_const_start) <= (1 << 15) ? 15 : (osee_all_const_stop - osee_all_const_start) <= (1 << 16) ? 16 : (osee_all_const_stop - osee_all_const_start) <= (1 << 17) ? 17 : (osee_all_const_stop - osee_all_const_start) <= (1 << 18) ? 18 : (osee_all_const_stop - osee_all_const_start) <= (1 << 19) ? 19 : (osee_all_const_stop - osee_all_const_start) <= (1 << 20) ? 20 : (osee_all_const_stop - osee_all_const_start) <= (1 << 21) ? 21 : (osee_all_const_stop - osee_all_const_start) <= (1 << 22) ? 22 : (osee_all_const_stop - osee_all_const_start) <= (1 << 23) ? 23 : (osee_all_const_stop - osee_all_const_start) <= (1 << 24) ? 24 : (osee_all_const_stop - osee_all_const_start) <= (1 << 25) ? 25 : (osee_all_const_stop - osee_all_const_start) <= (1 << 26) ? 26 : (osee_all_const_stop - osee_all_const_start) <= (1 << 27) ? 27 : (osee_all_const_stop - osee_all_const_start) <= (1 << 28) ? 28 : (osee_all_const_stop - osee_all_const_start) <= (1 << 29) ? 29 : (osee_all_const_stop - osee_all_const_start) <= (1 << 30) ? 30 : (osee_all_const_stop - osee_all_const_start) <= (1 << 31) ? 31 : -1);
    osee_all_const_size_to_align = 1 << osee_all_const_log2ceil_size;
    . = ALIGN(osee_all_const_size_to_align);
    osee_all_const_end = .;
    } > DDR
    core0_kernel_ram_start_align : {
    . = ALIGN(osee_core0_kernel_ram_size_to_align);
    osee_core0_kernel_ram_start = .;
    } > DDR
    OsApplication_Core0_ram_start_align : {
    osee_OsApplication_Core0_ram_start = .;
    } > DDR
    .OsApplication_Core0_bss : ALIGN(8) {
    *(osee_OsApplication_Core0_bss)
    *(*_OsApplication_Core0_bss)
    *(*_OsApplication_Core0_bss_64)
    *(*_OsApplication_Core0_bss_32)
    *(*_OsApplication_Core0_bss_ptr)
    *(*_OsApplication_Core0_bss_16)
    *(*_OsApplication_Core0_bss_8)
    *(*_OsApplication_Core0_bss_bool)
    *(*_OsApplication_Core0_bss_unspecified)
    *(*_OsApplication_Core0_postbuildbufbss)
    . = ALIGN(8);
    *(.bss.gEthRxBufMem)
    *(.bss.gEthTxBufMem)
    *(.bss.gEthCpswTxPkt)
    *(.bss.gEthCpswRxPkt)
    *(.bss.Cdd_IpcCommChBuf_0)
    . = ALIGN(8);
    *(.bss.Cdd_IpcCommChBuf_1)
    . = ALIGN(8);
    *(.bss.Cdd_IpcCommChBuf_2)
    . = ALIGN(8);
    *(ipc_data_buffer)
    . = ALIGN(8);
    *(.bss.Cdd_IpcRpMsgCtrlBuffer)
    . = ALIGN(8);
    *(.bss.*Ipc*)
    . = ALIGN(8);
    *(.bss.ddr)
    } > DDR
    .OsApplication_Core0_data : ALIGN(4) {
    osee_OsApplication_Core0_data_start = .;
    *(osee_OsApplication_Core0_data)
    *(*_OsApplication_Core0_data)
    *(*_OsApplication_Core0_data_64)
    *(*_OsApplication_Core0_data_32)
    *(*_OsApplication_Core0_data_ptr)
    *(*_OsApplication_Core0_data_16)
    *(*_OsApplication_Core0_data_8)
    *(*_OsApplication_Core0_data_bool)
    *(*_OsApplication_Core0_data_unspecified)
    *(*_OsApplication_Core0_postbuildbuf)
    *(*_OsApplication_Core0_postbuildbufdata)
    } > DDR
    . = ALIGN(64);
    OsApplication_Core0_ram_stop_align : {
    osee_OsApplication_Core0_ram_end = .;
    } > DDR
    .kernel_bss_cpu0 : ALIGN(8) {
    *(osee_core0_bss)
    *(*_core0_bss)
    . = ALIGN(8);
    } > DDR
    .kernel_data_cpu0 : ALIGN(4) {
    *(osee_core0_data)
    *(*_core0_data)
    } > DDR
    core0_kernel_ram_stop_align : {
    osee_core0_kernel_ram_stop = .;
    osee_core0_kernel_ram_log2ceil_size = ((osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 5) ? 5 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 6) ? 6 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 7) ? 7 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 8) ? 8 :(osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 9) ? 9 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 10) ? 10 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 11) ? 11 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 12) ? 12 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 13) ? 13 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 14) ? 14 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 15) ? 15 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 16) ? 16 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 17) ? 17 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 18) ? 18 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 19) ? 19 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 20) ? 20 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 21) ? 21 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 22) ? 22 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 23) ? 23 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 24) ? 24 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 25) ? 25 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 26) ? 26 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 27) ? 27 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 28) ? 28 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 29) ? 29 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 30) ? 30 : (osee_core0_kernel_ram_stop - osee_core0_kernel_ram_start) <= (1 << 31) ? 31 : -1);
    osee_core0_kernel_ram_size_to_align = 1 << osee_core0_kernel_ram_log2ceil_size;
    . = ALIGN(osee_core0_kernel_ram_size_to_align);
    osee_core0_kernel_ram_end = .;
    } > DDR
    kernel_ram_start_align : {
    . = ALIGN(osee_kernel_ram_size_to_align);
    osee_kernel_ram_start = .;
    } > SRAM
    .kernel_bss (NOLOAD) : ALIGN(8) {
    osEE_bss_start = .;
    *(.bss_cpu)
    *(ioc_kernel_bss)
    *(osee_kernel_bss)
    *(osee_core*_kernel_bss)
    *(*_kernel_bss)
    *(.gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN(8);
    osEE_bss_end = .;
    } > SRAM
    .kernel_bss_global (NOLOAD) : ALIGN(8) {
    *(osee_gbl_kernel_bss)
    } > SRAM
    .tbss : ALIGN(8) {
    *(.tbss)
    *(.tbss.*)
    *(.gnu.linkonce.tb.*)
    . = ALIGN(8);
    } > SRAM
    .sbss (NOLOAD) : ALIGN(8) {
    osEE_sbss_start = .;
    *(.sbss)
    *(.sbss.*)
    *(.gnu.linkonce.sb.*)
    . = ALIGN(8);
    osEE_sbss_end = .;
    } > SRAM
    .sbss2 : ALIGN(8) {
    *(.sbss2)
    *(.sbss2.*)
    *(.gnu.linkonce.sb2.*)
    . = ALIGN(8);
    } > SRAM
    .kernel_data : ALIGN(4) {
    osee_kernel_data_start = .;
    *(.data_cpu*)
    *(ioc_kernel_data)
    *(osee_kernel_data)
    *(osee_core*_kernel_data)
    *(*_kernel_data)
    *(.gnu.linkonce.d.*)
    } > SRAM
    .kernel_data_global : ALIGN(8) {
    *(osee_gbl_kernel_data)
    } > SRAM
    .data1 : ALIGN(4) {
    *(.data1)
    *(.data1.*)
    } > SRAM
    .sdata : ALIGN(4) {
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s.*)
    } > SRAM
    .sdata2 : ALIGN(4) {
    *(.sdata2)
    *(.sdata2.*)
    *(.gnu.linkonce.s2.*)
    } > SRAM
    .tdata : ALIGN(4) {
    *(.tdata)
    *(.tdata.*)
    *(.gnu.linkonce.td.*)
    } > SRAM
    .heap (NOLOAD) : ALIGN(64) {
    end = .;
    } > SRAM
    kernel_ram_stop_align : {
    osee_kernel_ram_stop = .;
    osee_kernel_ram_log2ceil_size = ((osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 5) ? 5 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 6) ? 6 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 7) ? 7 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 8) ? 8 :(osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 9) ? 9 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 10) ? 10 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 11) ? 11 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 12) ? 12 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 13) ? 13 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 14) ? 14 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 15) ? 15 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 16) ? 16 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 17) ? 17 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 18) ? 18 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 19) ? 19 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 20) ? 20 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 21) ? 21 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 22) ? 22 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 23) ? 23 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 24) ? 24 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 25) ? 25 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 26) ? 26 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 27) ? 27 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 28) ? 28 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 29) ? 29 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 30) ? 30 : (osee_kernel_ram_stop - osee_kernel_ram_start) <= (1 << 31) ? 31 : -1);
    osee_kernel_ram_size_to_align = 1 << osee_kernel_ram_log2ceil_size;
    . = ALIGN(osee_kernel_ram_size_to_align);
    osee_kernel_ram_end = .;
    } > SRAM
    api_ram_start_align : {
    . = ALIGN(osee_api_ram_size_to_align);
    osee_api_ram_start = .;
    } > SRAM
    .api_bss (NOLOAD) : ALIGN(8) {
    *(osee_api_bss)
    *(*_api_bss_32)
    *(*_api_bss_ptr)
    *(*_api_bss_16)
    *(*_api_bss_8)
    *(*_api_bss_bool)
    *(*_api_bss_unspecified)
    *(*_api_bss)
    *(*_api_postbuildbufbss)
    . = ALIGN(8);
    } > SRAM
    .bss (NOLOAD) : ALIGN(8) {
    *(.bss)
    *(.bss.*)
    } > SRAM
    .api_data : ALIGN(4) {
    osee_api_data_start = .;
    *(osee_api_data)
    *(*_api_data_ptr)
    *(*_api_data_32)
    *(*_api_data_16)
    *(*_api_data_8)
    *(*_api_data_bool)
    *(*_api_data_unspecified)
    *(*_api_data)
    *(*_api_postbuildbuf)
    *(*_api_postbuildbufdata)
    } > SRAM
    .data : ALIGN(8) {
    *(.data)
    *(.data.*)
    *(*_DATA_INIT_*_SECTION)
    } > SRAM
    api_ram_stop_align : {
    osee_api_ram_stop = .;
    osee_api_ram_log2ceil_size = ((osee_api_ram_stop - osee_api_ram_start) <= (1 << 5) ? 5 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 6) ? 6 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 7) ? 7 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 8) ? 8 :(osee_api_ram_stop - osee_api_ram_start) <= (1 << 9) ? 9 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 10) ? 10 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 11) ? 11 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 12) ? 12 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 13) ? 13 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 14) ? 14 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 15) ? 15 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 16) ? 16 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 17) ? 17 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 18) ? 18 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 19) ? 19 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 20) ? 20 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 21) ? 21 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 22) ? 22 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 23) ? 23 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 24) ? 24 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 25) ? 25 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 26) ? 26 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 27) ? 27 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 28) ? 28 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 29) ? 29 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 30) ? 30 : (osee_api_ram_stop - osee_api_ram_start) <= (1 << 31) ? 31 : -1);
    osee_api_ram_size_to_align = 1 << osee_api_ram_log2ceil_size;
    . = ALIGN(osee_api_ram_size_to_align);
    osee_api_ram_end = .;
    } > SRAM
    core0_api_ram_start_align : {
    . = ALIGN(osee_core0_api_ram_size_to_align);
    osee_core0_api_ram_start = .;
    } > SRAM
    .api_bss_cpu0 : ALIGN(8) {
    *(osee_core0_api_bss)
    *(*_core0_api_bss)
    . = ALIGN(8);
    } > SRAM
    .api_data_cpu0 : ALIGN(4) {
    *(osee_core0_api_data)
    *(*_core0_api_data)
    } > SRAM
    core0_api_ram_stop_align : {
    osee_core0_api_ram_stop = .;
    osee_core0_api_ram_log2ceil_size = ((osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 5) ? 5 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 6) ? 6 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 7) ? 7 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 8) ? 8 :(osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 9) ? 9 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 10) ? 10 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 11) ? 11 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 12) ? 12 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 13) ? 13 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 14) ? 14 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 15) ? 15 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 16) ? 16 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 17) ? 17 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 18) ? 18 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 19) ? 19 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 20) ? 20 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 21) ? 21 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 22) ? 22 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 23) ? 23 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 24) ? 24 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 25) ? 25 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 26) ? 26 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 27) ? 27 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 28) ? 28 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 29) ? 29 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 30) ? 30 : (osee_core0_api_ram_stop - osee_core0_api_ram_start) <= (1 << 31) ? 31 : -1);
    osee_core0_api_ram_size_to_align = 1 << osee_core0_api_ram_log2ceil_size;
    . = ALIGN(osee_core0_api_ram_size_to_align);
    osee_core0_api_ram_end = .;
    } > SRAM
    os_stack_start_align : {
    . = ALIGN(osee_os_stack_size_to_align);
    osee_os_stack_start = .;
    } > SRAM
    .stack (NOLOAD) : ALIGN(64) {
    *(.stack)
    } > SRAM
    . += 32;
    . = ALIGN(32);
    osee_OsApplication_Core0_stack_start = .;
    . = ALIGN(1024);
    .OsApplication_Core0_stack : ALIGN(4) {
    *(osee_OsApplication_Core0_stack)
    *(*_OsApplication_Core0_stack)
    } > SRAM
    . = ALIGN(32);
    osee_OsApplication_Core0_stack_end = .;
    . += 32;
    . = ALIGN(32);
    .cpu0.stack (NOLOAD): ALIGN(16) {
    osee_core0_stack_start = .;
    *(.stack_cpu0)
    *(.ustack_cpu0*)
    . = ALIGN(8);
    PROVIDE(osee_core0_sys_stack_top = .);
    . += Mode_SYS_Stack_Size;
    . = ALIGN(8);
    PROVIDE(osee_core0_sys_stack = .);
    PROVIDE(osee_core0_sys_stack_bottom = .);
    osEE_core0_svc_stack_top = .;
    . += Mode_SVC_Stack_Size;
    osEE_core0_svc_stack_bottom = .;
    . = ALIGN(8);
    PROVIDE(osee_core0_svc_stack = .);
    osEE_core0_irq_stack_top = .;
    . += Mode_IRQ_Stack_Size;
    osEE_core0_irq_stack_bottom = .;
    . = ALIGN(8);
    PROVIDE(osee_core0_irq_stack = .);
    osEE_core0_fiq_stack_top = .;
    . += Mode_FIQ_Stack_Size;
    osEE_core0_fiq_stack_bottom = .;
    . = ALIGN(8);
    PROVIDE(osee_core0_fiq_stack = .);
    osEE_core0_abt_stack_top = .;
    . += Mode_EXE_Stack_Size;
    osEE_core0_abt_stack_bottom = .;
    . = ALIGN(8);
    PROVIDE(osee_core0_abt_stack = .);
    osEE_core0_und_stack_top = .;
    . += Mode_EXE_Stack_Size;
    osEE_core0_und_stack_bottom = .;
    . = ALIGN(8);
    PROVIDE(osee_core0_und_stack = .);
    osee_core0_stack_end = .;
    } > SRAM
    os_stack_stop_align : {
    osee_os_stack_stop = .;
    osee_os_stack_log2ceil_size = ((osee_os_stack_stop - osee_os_stack_start) <= (1 << 5) ? 5 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 6) ? 6 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 7) ? 7 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 8) ? 8 :(osee_os_stack_stop - osee_os_stack_start) <= (1 << 9) ? 9 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 10) ? 10 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 11) ? 11 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 12) ? 12 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 13) ? 13 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 14) ? 14 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 15) ? 15 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 16) ? 16 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 17) ? 17 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 18) ? 18 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 19) ? 19 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 20) ? 20 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 21) ? 21 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 22) ? 22 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 23) ? 23 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 24) ? 24 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 25) ? 25 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 26) ? 26 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 27) ? 27 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 28) ? 28 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 29) ? 29 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 30) ? 30 : (osee_os_stack_stop - osee_os_stack_start) <= (1 << 31) ? 31 : -1);
    osee_os_stack_size_to_align = 1 << osee_os_stack_log2ceil_size;
    . = ALIGN(osee_os_stack_size_to_align);
    osee_os_stack_end = .;
    } > SRAM


    .caldata :
    {
    __DS_CALDATA_START = .;
    *(.caldata.asw)
    . = ALIGN(8);
    __DS_CALDATA_LVL2_START = .;

    *(.caldata.lvl2)
    . = ALIGN(8);
    __DS_CALDATA_LVL2_END = . - 1;

    *(.caldata)
    . = ALIGN(8);
    __DS_CALDATA_END = . - 1;
    } > DDR_DS

    /***********************************************************/
    /* virtual sections without memory */
    /***********************************************************/
    .debug_aranges 0 : { *(.debug_aranges) }
    .debug_macinfo 0 : { *(.debug_macinfo) }
    .debug_abbrev 0 : { *(.debug_abbrev) }
    .debug_info 0 : { *(.debug_info) }
    .debug_line 0 : { *(.debug_line) }

    .debug_frame 0 : { *(.debug_frame) }
    .debug_ranges 0 : { *(.debug_ranges) }
    .debug_str 0 : { *(.debug_str) }
    .debug_loc 0 : { *(.debug_loc) }

    .ARM.attributes 0 : { *(.ARM.attributes)}

    .rel.plt 0 : { *(.rel.plt) }
    .rel.dyn 0 : { *(.rel.dyn) }
    .symtab 0 : { *(.symtab) }
    .symtab_shndxr 0 : { *(.symtab_shndxr) }
    .shstrtab 0 : { *(.shstrtab) }
    .strtab 0 : { *(.strtab) }

    .unspecified_sections : { *(*) } > must_be_empty
    }

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