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TRM 265页第二段:Although the GPMC interface can drive up to seven chip-selects, the frequency specified for this interface is for a specific load. If this load is exceeded, the aximum frequency cannot be reached. One solution is to implement a board with buffers, to allow the slowest device to maintain the total load on the lines. 我们现在计划GPMC总线上接2个器件:NandFlash,SRAM,如果此时再接一个较慢的器件,操作一次可能等待时间较长,必须使用buffer吗?如果不用,就是总线速度受影响还是影响功能?