各位大神好：
我碰到一个问题，在论坛上找到一个几年前的问题类似的帖子，但是帖子没有提供最终的解决方案，我再发一次，希望有大神能给出解决方案。
在连接C6657所选的核时，会加载gel文件到相应的核，并在核中执行，我们的问题是连接核1时能正常加载并执行gel，连接核0执行gel时出现报错。
gel文件中有关于核的判断，我在用核0加载时将文件中的核判断改成了0，在用核1加载时将核判断改成了1。
问题貌似是出在DDR3的寄存器的操作上。
核1能够加载并正常运行gel，log如下：
C66xx_1: GEL Output:
Connecting Target...
C66xx_1: GEL Output: DSP core #1
C66xx_1: GEL Output: C6657L GEL file Ver is 1.00300002
C66xx_1: GEL Output: Global Default Setup...
C66xx_1: GEL Output: Setup Cache...
C66xx_1: GEL Output: L1P = 32K
C66xx_1: GEL Output: L1D = 32K
C66xx_1: GEL Output: L2 = ALL SRAM
C66xx_1: GEL Output: Setup Cache... Done.
C66xx_1: GEL Output: Main PLL (PLL1) Setup ...
C66xx_1: GEL Output: PLL in Bypass ...
C66xx_1: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_1: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_1: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_1: GEL Output: PLL1 Setup... Done.
C66xx_1: GEL Output: Power on all PSC modules and DSP domains...
C66xx_1: GEL Output: Set_PSC_State... Timeout Error #03 pd=12, md=4!
C66xx_1: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_1: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_1: GEL Output: DDR3 PLL Setup... Done.
C66xx_1: GEL Output: DDR3 Init begin (1333 auto)
C66xx_1: GEL Output: XMC Setup ... Done
C66xx_1: GEL Output:
DDR3 initialization is complete.
C66xx_1: GEL Output: DDR3 Init done
C66xx_1: GEL Output: DDR3 memory test... Started
C66xx_1: GEL Output: DDR3 memory test... Passed
C66xx_1: GEL Output: PLL and DDR3 Initialization completed(0) ...
C66xx_1: GEL Output: Enabling EDC ...
C66xx_1: GEL Output: L1P error detection logic is enabled.
C66xx_1: GEL Output: L2 error detection/correction logic is enabled.
C66xx_1: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_1: GEL Output: Enabling EDC ...Done
C66xx_1: GEL Output: Global Default Setup... Done.
核0加载gel文件执行时出现以下的报错：
