TI 工程师您好:
我司使用贵公司的66AK2H12开发一个电路板,使用示波器测量PCIe Lane 0 Tx 的差分信号,从示波器看到幅度约2V 这与PCIe 2.0协议中的描述不太一样,请问主要是什么原因呢?
谢谢!
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
TI 工程师您好:
我司使用贵公司的66AK2H12开发一个电路板,使用示波器测量PCIe Lane 0 Tx 的差分信号,从示波器看到幅度约2V 这与PCIe 2.0协议中的描述不太一样,请问主要是什么原因呢?
谢谢!
请参考下面的帖子
TI has performed the simulation and system characterization to ensure all PCIe interface timings are met; therefore, no electrical data/timing information is supplied in data manual for PCIe interface.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/403483/tms320c6655-6657-pcie-serdes-differential-i-o-voltage-levels-expected