AM625: am6254 spi demo 测试异常

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https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1181330/am625-am6254-spi-demo

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I am assuming you are talking about mcspi performance 8 bit?

Have you opted for MCU or Main Domain SPI peripheral?

Please confirm on the above, so that I can proceed looking into the same.

1 我测试的是mcspi performance 8 bit 这个例程
2 我测试的mcu的管脚，例程中的example.syscfg文件没有改变，而且测试的mcspi_loopback 这个例程，不论是内回环还是我修改example.syscfg文件改为外部端子发送接收，都没有问题，应该能证明硬件没有问题。

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请看下面工程师的回复，可能需要花点时间验证一下，请耐心等待。另外，麻烦回复一下工程师的问题。

I have recreated your issue. I am also getting the same output as yours and I see it says, "Data Mismatch at offset 1".

I am working on it, and I will come up with a fix to it. (Please allow me sometime for the same, as I will debug and try to find the problem at the granular level)

Could you also answer the following:

1. Which core are you using, is it M4 or R5? 

2. Is it FreeRtos or Baremetal?

1 使用的M4核，官方的例程没有修改，默认的就是M4核
2 FreeRTOS和裸跑系统的两个例程都测试了 效果是一样的，都是收发不一致。

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I have noticed that the problem with the data mismatch at all the offsets has been persistent in the previous release as well; for example the release 8.4, and the current 8.5.

I am going to talk with the respective team and try to find out where the problem really is.

好的 后续我会在英文论坛直接回复，感谢感谢。

好的，感谢！