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仿真器的XDS100v2的EMU0/EMU1是如何工作的?

例如使用XDS100v2,在其连接配置高级中有“The JTAG nTRST Boot-Mode”选项,官方文档解析是“Support for “JTAG reset”/"wait-in-reset" boot-modes using the two EMU pins sampled by the nTRST pin.”,假若选择“Enabled - EMU1 is high, EMU0 is low”选项,在仿真器运行期间EMU0/EMU1又是如何动作的?EMU动作后是持久保持还是有一定保持时间的?