您好，
EDMA 有个触发事件 EXTINT4 ，这个事件怎么产生呢，管脚 GP4 高电平？低电平？上升沿？下降沿？
在哪里配置呢，datasheet上只说了这个事件触发DMA，但是什么情况下这个事件发生呢？
EXTPOL寄存器可以改变中断的触发方式，那么EDMA呢，datasheet上写了这么一句话：
EXTPOL only affects interrupts to
the CPU and has no effect on DMA events.
我写了一个程序，测试结果为，给ＧＰ４单个上升沿，能触发一次ＤＭＡ；给ＧＰ４单个下降沿沿，也能触发一次ＤＭＡ；若连续给几个上升沿，下降沿，结果并不是每个沿都能触发，程序如下
/*------------------------------------------------------------------------------
*上海宇志通信技术有限公司 www.caspl.cn
*------------------------------------------------------------------------------
*阵列信号处理平台-ASP1216测试例程
*------------------------------------------------------------------------------*/
#include <stdio.h>
#include <csl.h>
#include <csl_cache.h>
#include <csl_edma.h>
#include <csl_irq.h>
#include "reg6713.h"
#define TCCINTNUM 10
#define BUFF_SZ 64
//define soure and destination buffer
#pragma DATA_SECTION (SoureBuf, ".buffers");
#pragma DATA_SECTION (DestinationBuf, ".buffers");
#pragma DATA_ALIGN(SoureBuf,128);
#pragma DATA_ALIGN(DestinationBuf,128);
int SoureBuf[BUFF_SZ];
int DestinationBuf[BUFF_SZ];
int j=0;
int aaaa;
extern far void vectors();
void setupInterrupts(void);
void stopEdma(void); /* function used to stop EDMA */
EDMA_Handle hEdma; /* Handle for the EDMA channel */
EDMA_Config cfgEdmaTrans = {
EDMA_OPT_RMK( /* Making Options parameter register - EDMA_OPT */
EDMA_OPT_PRI_LOW, /* Priority levels for EDMA events:-
EDMA_OPT_PRI_LOW - Low priority EDMA transfer
EDMA_OPT_PRI_HIGH - High priority EDMA transfer*/
EDMA_OPT_ESIZE_32BIT,/* Element size :-
EDMA_OPT_ESIZE_32BIT - 32 bit word
EDMA_OPT_ESIZE_16BIT - 16 bit word
EDMA_OPT_ESIZE_8BIT - 8 bit word */
EDMA_OPT_2DS_NO, /* Source dimension :-
EDMA_OPT_2DS_NO - 1-dimensional source
EDMA_OPT_2DS_YES - 2-dimensional source */
EDMA_OPT_SUM_INC, /* Source address update mode :-
EDMA_OPT_SUM_NONE - Fixed address mode
EDMA_OPT_SUM_INC - Increment address mode
EDMA_OPT_SUM_DEC - Decrement address mode
EDMA_OPT_SUM_IDX - Address modified by element
index or frame Index */
EDMA_OPT_2DD_NO, /* Destination dimension :-
EDMA_OPT_2DD_NO - 1-dimensional source
EDMA_OPT_2DD_YES - 2-dimensional source */
EDMA_OPT_DUM_INC, /* Destination address update mode :-
EDMA_OPT_DUM_NONE - Fixed address mode
EDMA_OPT_DUM_INC - Increment address mode
EDMA_OPT_DUM_DEC - Decrement address mode
EDMA_OPT_DUM_IDX - Address modified by element
index or frame Index */
EDMA_OPT_TCINT_YES, /* Transfer complete interrupt :-
EDMA_OPT_TCINT_NO - Indication disabled
EDMA_OPT_TCINT_YES - Indication enabled */
EDMA_OPT_TCC_OF(TCCINTNUM),/* Transfer complete code */
EDMA_OPT_LINK_NO, /* Linking of event parameters
EDMA_OPT_LINK_NO - Disabled
EDMA_OPT_LINK_YES - Enabled */
EDMA_OPT_FS_NO /* Frame synchronization
EDMA_OPT_FS_NO - Channel is element/array
synchronized
EDMA_OPT_FS_YES - Channel is frame synchronized*/
),
EDMA_SRC_OF(SoureBuf),/* Source address register
&ping_data - source address */
EDMA_CNT_OF(1), /* Transfer count parameter
BUFF_SZ - buffer sizes in # of ints */
EDMA_DST_OF(DestinationBuf), /* Destination address parameter
ping - destination address */
EDMA_IDX_OF(0x00000004),/* Index parameter */
EDMA_RLD_OF(0x00010000) /* Count reload/link parameter */
};
void main()
{
int i;
/* initialize the CSL library */
//CSL_init();
/* Configure L2 for 64K Cache and enable caching of external memory*/
/*-------------EMIF global Registers Configration-------*/
*(int *)EMIF_GCTL = 0x00003060;/* EMIF global control register */
*(int *)EMIF_CE1 = 0xFFFFFF23; /* CE1 - 16-bit asynch access */
*(int *)EMIF_CE0 = 0xFFFFFF30; /* CE0 - SDRAM */
*(int *)EMIF_CE2 = 0xFFFFFF23; /* CE2 - 32-bit asynch on daughterboard */
*(int *)EMIF_CE3 = 0xFFFFFF23; /* CE3 - 32-bit asynch on daughterboard */
*(int *)EMIF_SDRAMCTL = 0x57117000; /* SDRAM control register (100 MHz)*/
*(int *)EMIF_SDRAMTIMING = 0x0000061a; /* SDRAM Timing register */
/*--------------------------------------------------*/
// *(int *)GPPOL = 0x00000010;
*(int *)EXTPOL = 0x0000000F;
//Set Cahe
CACHE_setL2Mode(CACHE_64KCACHE);
CACHE_enableCaching(CACHE_CE30);
//缓冲区初始化
j=j+10;
for(i=0;i<BUFF_SZ;i++)
{
SoureBuf[i]=0x0001*(i+j);
}
//设置中断
setupInterrupts();
EDMA_clearPram(0x00000000);
hEdma = EDMA_open(EDMA_CHA_EXTINT4, EDMA_OPEN_RESET); //4通道
//hEdma = EDMA_open(EDMA_CHA_AXEVTE0, EDMA_OPEN_RESET);
EDMA_config(hEdma, &cfgEdmaTrans);
/* Enable the related interrupts */
IRQ_enable(IRQ_EVT_DMAINT0);
EDMA_intDisable(TCCINTNUM);
EDMA_intClear(TCCINTNUM);
EDMA_intEnable(TCCINTNUM);
CACHE_wbInvL2(SoureBuf, 4*BUFF_SZ, CACHE_WAIT);
CACHE_wbInvL2(DestinationBuf, 4*BUFF_SZ, CACHE_WAIT);
/* Enable the EDMA channel */
EDMA_enableChannel(hEdma);
while(1);
}
void setupInterrupts(void)
{
IRQ_setVecs(vectors); /* point to the IRQ vector table */
IRQ_nmiEnable();
IRQ_globalEnable();
IRQ_map(IRQ_EVT_DMAINT0, 10); // EDMA interrupt
IRQ_reset(IRQ_EVT_DMAINT0);
} /* End of SetInterruptsEdma() */
interrupt void
c_int08(void)
{
int i;
j++;
CACHE_wbInvL2(SoureBuf, 4*BUFF_SZ, CACHE_WAIT);
/* Clear the pending interrupt from the EDMA interrupt pending register */
EDMA_intClear(TCCINTNUM);
// for(i=0;i<BUFF_SZ;i++)
// {
// SoureBuf[i]=0x0001*(i+j);
// }
// EDMA_config(hEdma, &cfgEdmaTrans);
return;
}
谢谢您
