现在自己做的板子网口部分是参考EVM_SK设计的，AR8031，现在移植了linux3.2.0的网口驱动只有一个正常工作，另一个怎么也ping不通，link，设置ip都没问题，我发现手动启用两个网卡，返回的id都是一样的0x4dd074，见附件，希望有知道解决办法的高手帮忙解答，谢谢啦.
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/*
* Code for AM335X EVM.
*
* Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/i2c/at24.h>
#include <linux/phy.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/wl12xx.h>
#include <linux/ethtool.h>
#include <linux/mfd/tps65910.h>
#include <linux/mfd/tps65217.h>
#include <linux/pwm_backlight.h>
#include <linux/input/ti_tsc.h>
#include <linux/platform_data/ti_adc.h>
#include <linux/mfd/ti_tscadc.h>
#include <linux/reboot.h>
#include <linux/pwm/pwm.h>
#include <linux/rtc/rtc-omap.h>
#include <linux/opp.h>
/* LCD controller is similar to DA850 */
#include <video/da8xx-fb.h>
#include <mach/hardware.h>
#include <mach/board-am335xevm.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/hardware/asp.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>
#include <plat/irqs.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/lcdc.h>
#include <plat/usb.h>
#include <plat/mmc.h>
#include <plat/emif.h>
#include <plat/nand.h>
#include "board-flash.h"
#include "cpuidle33xx.h"
#include "mux.h"
#include "devices.h"
#include "hsmmc.h"
/* Convert GPIO signal to GPIO pin number */
#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
/* BBB PHY IDs */
#define BBB_PHY_ID 0x7c0f1
#define BBB_PHY_MASK 0xfffffffe
/* AM335X EVM Phy ID and Debug Registers */
#define AM335X_EVM_PHY_ID 0x4dd074
#define AM335X_EVM_PHY_MASK 0xfffffffe
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY BIT(8)
/*
#define CONFIG_DH_320_240 1
#define CONFIG_DH_480_272 2
#define CONFIG_DH_800_480 3
#define CONFIG_DH_800_600 4*/
static const struct display_panel disp_panel = {
WVGA,
32,
16,//32, --czx
COLOR_ACTIVE,
};
/* LCD backlight platform Data */
#define AM335X_BACKLIGHT_MAX_BRIGHTNESS 100
#define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS 100
#define AM335X_PWM_PERIOD_NANO_SECONDS (5000 * 10)
static struct platform_pwm_backlight_data am335x_backlight_data0 = {
.pwm_id = "ecap.0",
.ch = -1,
.lth_brightness = 21,
.max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
.dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
.pwm_period_ns = AM335X_PWM_PERIOD_NANO_SECONDS,
};
static struct platform_pwm_backlight_data am335x_backlight_data2 = {
.pwm_id = "ecap.2",
.ch = -1,
.lth_brightness = 21,
.max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
.dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
.pwm_period_ns = AM335X_PWM_PERIOD_NANO_SECONDS,
};
static struct lcd_ctrl_config lcd_cfg = {
//#if defined (CONFIG_DH_320_240)||(CONFIG_DH_480_272)||(CONFIG_DH_800_480)||(CONFIG_DH_800_600)
/*&disp_panel,
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 16,//32,--czx
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,*/
//#elif defined CONFIG_VGA
&disp_panel,
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 16,//32,--czx
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
//#endif
};
struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
.manu_name = "ThreeFive",
.controller_data = &lcd_cfg,
.type = "TFC_S9700RTWV35TR_01B",
};
struct da8xx_lcdc_platform_data NHD_480272MF_ATXI_pdata = {
.manu_name = "NHD",
.controller_data = &lcd_cfg,
.type = "NHD-4.3-ATXI#-T-1",
};
// --czx
struct da8xx_lcdc_platform_data YL_LCD_pdata = {
.manu_name = "DH",
.controller_data = &lcd_cfg,
#if defined (CONFIG_DH_320_240)
.type = "YL_LCD35",
#elif defined (CONFIG_DH_480_272)
.type = "YL_LCD43",
#elif defined (CONFIG_DH_800_480)
.type = "YL_LCD70",
#elif defined CONFIG_DH_800_600
.type = "YL_LCD80",
#elif defined CONFIG_VGA
.type = "YL_VGA",
#endif
};
//end
#include "common.h"
/* TSc controller */
static struct tsc_data am335x_touchscreen_data = {
.wires = 4,
.x_plate_resistance = 200,
.steps_to_configure = 5,
};
static struct adc_data am335x_adc_data = {
.adc_channels = 4,
};
static struct mfd_tscadc_board tscadc = {
.tsc_init = &am335x_touchscreen_data,
.adc_init = &am335x_adc_data,
};
static u8 am335x_evm_sk_iis_serializer_direction1[] = {
RX_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
};
static struct snd_platform_data am335x_evm_snd_data1 = {
.tx_dma_offset = 0x46400000, /* McASP1 */
.rx_dma_offset = 0x46400000,
.op_mode = DAVINCI_MCASP_IIS_MODE,
.num_serializer = ARRAY_SIZE(am335x_evm_sk_iis_serializer_direction1),
.tdm_slots = 2,
.serial_dir = am335x_evm_sk_iis_serializer_direction1,
.asp_chan_q = EVENTQ_2,
.version = MCASP_VERSION_3,
.txnumevt = 1,
.rxnumevt = 1,
.get_context_loss_count =
omap_pm_get_dev_context_loss_count,
};
static struct snd_platform_data am335x_evm_sk_snd_data1 = {
.tx_dma_offset = 0x46400000, /* McASP1 */
.rx_dma_offset = 0x46400000,
.op_mode = DAVINCI_MCASP_IIS_MODE,
.num_serializer = ARRAY_SIZE(am335x_evm_sk_iis_serializer_direction1),
.tdm_slots = 2,
.serial_dir = am335x_evm_sk_iis_serializer_direction1,
.asp_chan_q = EVENTQ_2,
.version = MCASP_VERSION_3,
.txnumevt = 1,
.rxnumevt = 1,
.get_context_loss_count =
omap_pm_get_dev_context_loss_count,
};
static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = GPIO_TO_PIN(0, 6),
.gpio_wp = -EINVAL,//GPIO_TO_PIN(3, 18),//--czx
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
},
{
.mmc = 0, /* will be set at runtime */
},
{
.mmc = 0, /* will be set at runtime */
},
{} /* Terminator */
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/*
* Setting SYSBOOT[5] should set xdma_event_intr0 pin to mode 3 thereby
* allowing clkout1 to be available on xdma_event_intr0.
* However, on some boards (like EVM-SK), SYSBOOT[5] isn't properly
* latched.
* To be extra cautious, setup the pin-mux manually.
* If any modules/usecase requries it in different mode, then subsequent
* module init call will change the mux accordingly.
*/
AM33XX_MUX(XDMA_EVENT_INTR0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT),
AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
AM33XX_INPUT_EN |AM33XX_PIN_OUTPUT),
AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
/* module pin mux structure */
struct pinmux_config {
const char *string_name; /* signal name format */
int val; /* Options for the mux register value */
};
struct evm_dev_cfg {
void (*device_init)(int evm_id, int profile);
/*
* If the device is required on both baseboard & daughter board (ex i2c),
* specify DEV_ON_BASEBOARD
*/
#define DEV_ON_BASEBOARD 0
#define DEV_ON_DGHTR_BRD 1
u32 device_on;
u32 profile; /* Profiles (0-7) in which the module is present */
};
/* AM335X - CPLD Register Offsets */
#define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
#define CPLD_DEVICE_ID 0x04 /* CPLD identification */
#define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
#define CPLD_CFG_REG 0x10 /* Configuration Register */
static struct i2c_client *cpld_client;
static u32 am335x_evm_id;
static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
};
/*
* EVM Config held in On-Board eeprom device.
*
* Header Format
*
* Name Size Contents
* (Bytes)
*-------------------------------------------------------------
* Header 4 0xAA, 0x55, 0x33, 0xEE
*
* Board Name 8 Name for board in ASCII.
* Example "A33515BB" = "AM335x 15x15 Base Board"
*
* Version 4 Hardware version code for board in ASCII.
* "1.0A" = rev.01.0A
*
* Serial Number 12 Serial number of the board. This is a 12
* character string which is WWYY4P16nnnn, where
* WW = 2 digit week of the year of production
* YY = 2 digit year of production
* nnnn = incrementing board number
*
* Configuration option 32 Codes(TBD) to show the configuration
* setup on this board.
*
* Available 32720 Available space for other non-volatile data.
*/
struct am335x_evm_eeprom_config {
u32 header;
u8 name[8];
char version[4];
u8 serial[12];
u8 opt[32];
};
/*
* EVM Config held in daughter board eeprom device.
*
* Header Format
*
* Name Size Contents
* (Bytes)
*-------------------------------------------------------------
* Header 4 0xAA, 0x55, 0x33, 0xEE
*
* Board Name 8 Name for board in ASCII.
* example "A335GPBD" = "AM335x
* General Purpose Daughterboard"
*
* Version 4 Hardware version code for board in
* in ASCII. "1.0A" = rev.01.0A
* Serial Number 12 Serial number of the board. This is a 12
* character string which is: WWYY4P13nnnn, where
* WW = 2 digit week of the year of production
* YY = 2 digit year of production
* nnnn = incrementing board number
* Configuration Option 32 Codes to show the configuration
* setup on this board.
* CPLD Version 8 CPLD code version for board in ASCII
* "CPLD1.0A" = rev. 01.0A of the CPLD
* Available 32700 Available space for other non-volatile
* codes/data
*/
struct am335x_eeprom_config1 {
u32 header;
u8 name[8];
char version[4];
u8 serial[12];
u8 opt[32];
u8 cpld_ver[8];
};
static struct am335x_evm_eeprom_config config;
static struct am335x_eeprom_config1 config1;
static bool daughter_brd_detected;
#define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
#define EEPROM_NO_OF_MAC_ADDR 3
static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
#define AM335X_EEPROM_HEADER 0xEE3355AA
static int am33xx_evmid = -EINVAL;
/*
* am335x_evm_set_id - set up board evmid
* @evmid - evm id which needs to be configured
*
* This function is called to configure board evm id.
*/
void am335x_evm_set_id(unsigned int evmid)
{
am33xx_evmid = evmid;
return;
}
/*
* am335x_evm_get_id - returns Board Type (EVM/BB/EVM-SK ...)
*
* Note:
* returns -EINVAL if Board detection hasn't happened yet.
*/
int am335x_evm_get_id(void)
{
return am33xx_evmid;
}
EXPORT_SYMBOL(am335x_evm_get_id);
/* current profile if exists else PROFILE_0 on error */
static u32 am335x_get_profile_selection(void)
{
int val = 0;
if (!cpld_client)
/* error checking is not done in func's calling this routine.
so return profile 0 on error */
return 0;
val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
if (val < 0)
return 0; /* default to Profile 0 on Error */
else
return val & 0x7;
}
static struct pinmux_config haptics_pin_mux[] = {
{"gpmc_ad9.ehrpwm2B", OMAP_MUX_MODE4 |
AM33XX_PIN_OUTPUT},
{NULL, 0},
};
/* Module pin mux for LCDC */
static struct pinmux_config lcdc_pin_mux[] = {
{"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
| AM33XX_PULL_DISA},
{"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
{"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
{"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
{"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
{NULL, 0},
};
static struct pinmux_config tsc_pin_mux[] = {
{"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
{"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
{"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
{"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
{"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
{"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
{NULL, 0},
};
/* Pin mux for nand flash module */
static struct pinmux_config nand_pin_mux[] = {
{"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
{"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
{"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
{"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
{"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
{NULL, 0},
};
/* Module pin mux for rgmii1 */
static struct pinmux_config rgmii1_pin_mux[] = {
{"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
{NULL, 0},
};
/* Module pin mux for rgmii2 */
static struct pinmux_config rgmii2_pin_mux[] = {
{"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
{NULL, 0},
};
static struct pinmux_config i2c0_pin_mux[] = {
{"i2c0_sda.i2c0_sda", OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
{"i2c0_scl.i2c0_scl", OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
{NULL, 0},
};
/* Module pin mux for mcasp1 */
static struct pinmux_config mcasp1_pin_mux[] = {
{"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
{"rmii1_refclk.mcasp1_ahclkx", OMAP_MUX_MODE6 |AM33XX_PIN_OUTPUT},
{"mcasp0_ahclkx.mcasp1_axr1", OMAP_MUX_MODE3 |AM33XX_PIN_INPUT_PULLDOWN},
{NULL, 0},
};
/* Module pin mux for mmc0 */
static struct pinmux_config mmc0_common_pin_mux[] = {
{"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{NULL, 0},
};
static struct pinmux_config uart4_pin_mux[] = {
{"uart0_ctsn.uart4_rxd", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
{"uart0_rtsn.uart4_txd", OMAP_MUX_MODE1 | AM33XX_PULL_ENBL},
{NULL, 0},
};
static struct pinmux_config d_can_gp_pin_mux[] = {
{"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
{"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
{NULL, 0},
};
/* pinmux for gpio based key */
static struct pinmux_config gpio_keys_pin_mux[] = { //lh
{"mcasp0_aclkx.gpio3_14", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},//K1
{"mcasp0_fsx.gpio3_15", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
{"mcasp0_axr0.gpio3_16", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
{"mcasp0_aclkr.gpio3_18", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
{NULL, 0},
};
/* pinmux for led device */
static struct pinmux_config gpio_led_mux[] = { //lh
{"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
{"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
{NULL, 0},
};
/*
* @pin_mux - single module pin-mux structure which defines pin-mux
* details for all its pins.
*/
static void setup_pin_mux(struct pinmux_config *pin_mux)
{
int i;
for (i = 0; pin_mux->string_name != NULL; pin_mux++)
omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
}
static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
/*.buttons = am335x_evm_volume_gpio_buttons,
.nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),*/
};
static struct platform_device am335x_evm_volume_keys = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &am335x_evm_volume_gpio_key_info,
},
};
static void volume_keys_init(int evm_id, int profile)
{
int err;
//setup_pin_mux(volume_keys_pin_mux);
err = platform_device_register(&am335x_evm_volume_keys);
if (err)
pr_err("failed to register matrix keypad (2x3) device\n");
}
/*
* @evm_id - evm id which needs to be configured
* @dev_cfg - single evm structure which includes
* all module inits, pin-mux defines
* @profile - if present, else PROFILE_NONE
* @dghtr_brd_flg - Whether Daughter board is present or not
*/
static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
int profile)
{
int i;
am335x_evm_set_id(evm_id);
/*
* Only General Purpose & Industrial Auto Motro Control
* EVM has profiles. So check if this evm has profile.
* If not, ignore the profile comparison
*/
/*
* If the device is on baseboard, directly configure it. Else (device on
* Daughter board), check if the daughter card is detected.
*/
if (profile == PROFILE_NONE) {
for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
pr_info("_configure_device %d \n",i);
if (dev_cfg->device_on == DEV_ON_BASEBOARD)
dev_cfg->device_init(evm_id, profile);
else if (daughter_brd_detected == true)
dev_cfg->device_init(evm_id, profile);
}
} else {
for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
pr_info("_configure_device %d \n",i);
if (dev_cfg->profile & profile) {
if (dev_cfg->device_on == DEV_ON_BASEBOARD)
dev_cfg->device_init(evm_id, profile);
else if (daughter_brd_detected == true)
dev_cfg->device_init(evm_id, profile);
}
}
}
}
/* pinmux for usb0 drvvbus */
static struct pinmux_config usb0_pin_mux[] = {
{"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
{NULL, 0},
};
/* pinmux for usb1 drvvbus */
static struct pinmux_config usb1_pin_mux[] = {
{"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
{NULL, 0},
};
/* Module pin mux for eCAP0 */
static struct pinmux_config ecap0_pin_mux[] = {
{"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
{NULL, 0},
};
//#define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
//#define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
//#define AM335XEVM_SK_WLAN_IRQ_GPIO GPIO_TO_PIN(0, 31)
struct wl12xx_platform_data am335xevm_wlan_data = {
/*.irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
.board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
/*.bt_enable_gpio = GPIO_TO_PIN(3, 21),
.wlan_enable_gpio = GPIO_TO_PIN(1, 16),*/
};
static struct pinmux_config uart1_wl12xx_pin_mux[] = {
//{"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
//{"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
{"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
{NULL, 0},
};
static struct pinmux_config wl12xx_pin_mux[] = {
//{"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
//{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
//{"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},
{NULL, 0},
};
static struct pinmux_config wl12xx_pin_mux_sk[] = {
//{"gpmc_wpn.gpio0_31", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
//{"gpmc_csn0.gpio1_29", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},
//{"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
{NULL, 0},
};
static bool backlight_enable;
static void enable_ecap0(int evm_id, int profile)
{
backlight_enable = true;
setup_pin_mux(ecap0_pin_mux);
}
static void enable_ecap2(int evm_id, int profile)
{
backlight_enable = true;
//setup_pin_mux(ecap2_pin_mux);
}
/* Setup pwm-backlight */
static struct platform_device am335x_backlight = {
.name = "pwm-backlight",
.id = -1,
.dev = {
.platform_data = &am335x_backlight_data0,
},
};
static struct pwmss_platform_data pwm_pdata[3] = {
{
.version = PWM_VERSION_1,
},
{
.version = PWM_VERSION_1,
},
{
.version = PWM_VERSION_1,
},
};
static int __init backlight_init(void)
{
int status = 0;
if (backlight_enable) {
int ecap_index = 0;
switch (am335x_evm_get_id()) {
case GEN_PURP_EVM:
case GEN_PURP_DDR3_EVM:
ecap_index = 0;
break;
case EVM_SK:
/*
* Invert polarity of PWM wave from ECAP to handle
* backlight intensity to pwm brightness
*/
ecap_index = 2;
pwm_pdata[ecap_index].chan_attrib[0].inverse_pol = true;
am335x_backlight.dev.platform_data =
&am335x_backlight_data2;
break;
default:
pr_err("%s: Error on attempting to enable backlight,"
" not supported\n", __func__);
return -EINVAL;
}
am33xx_register_ecap(ecap_index, &pwm_pdata[ecap_index]);
platform_device_register(&am335x_backlight);
}
return status;
}
late_initcall(backlight_init);
static int __init conf_disp_pll(int rate)
{
struct clk *disp_pll;
int ret = -EINVAL;
disp_pll = clk_get(NULL, "dpll_disp_ck");
if (IS_ERR(disp_pll)) {
pr_err("Cannot clk_get disp_pll\n");
goto out;
}
ret = clk_set_rate(disp_pll, rate);
clk_put(disp_pll);
out:
return ret;
}
static void lcdc_init(int evm_id, int profile)
{
struct da8xx_lcdc_platform_data *lcdc_pdata;
setup_pin_mux(lcdc_pin_mux);
pr_info("lcdc_init ********************************** \n");
if (conf_disp_pll(300000000)) {
pr_info("Failed configure display PLL, not attempting to"
"register LCDC\n");
return;
}
switch (evm_id) {
case GEN_PURP_EVM:
case GEN_PURP_DDR3_EVM:
lcdc_pdata = &TFC_S9700RTWV35TR_01B_pdata;
break;
case EVM_SK:
//lcdc_pdata = &NHD_480272MF_ATXI_pdata;
lcdc_pdata = &YL_LCD_pdata;
break;
default:
pr_err("LCDC not supported on this evm (%d)\n",evm_id);
return;
}
lcdc_pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
if (am33xx_register_lcdc(lcdc_pdata))
pr_info("Failed to register LCDC device\n");
return;
}
static void mfd_tscadc_init(int evm_id, int profile)
{
int err;
pr_info("mfd_tscadc_init ********************************** \n");
err = am33xx_register_mfd_tscadc(&tscadc);
if (err)
pr_err("failed to register touchscreen device\n");
}
static void rgmii1_init(int evm_id, int profile)
{
pr_info("rgmii1_init ********************************** \n");
setup_pin_mux(rgmii1_pin_mux);
return;
}
static void rgmii2_init(int evm_id, int profile)
{
pr_info("rgmii2_init ********************************** \n");
setup_pin_mux(rgmii2_pin_mux);
return;
}
static void usb0_init(int evm_id, int profile)
{
setup_pin_mux(usb0_pin_mux);
return;
}
static void usb1_init(int evm_id, int profile)
{
setup_pin_mux(usb1_pin_mux);
return;
}
/* setup uart4 */ //lh
static void uart4_init(int evm_id, int profile)
{
pr_info("uart4_init ********************************** \n");
setup_pin_mux(uart4_pin_mux);
return;
}
/* setup uart3 */
static void uart3_init(int evm_id, int profile)
{
pr_info("uart3_init ********************************** \n");
//setup_pin_mux(uart3_pin_mux);
return;
}
/* setup uart2 */
static void uart2_init(int evm_id, int profile)
{
pr_info("uart2_init ********************************** \n");
//setup_pin_mux(uart2_pin_mux);
return;
}
/*
* gpio0_7 was driven HIGH in u-boot before DDR configuration
*
* setup gpio0_7 for EVM-SK 1.2
*/
static void gpio_ddr_vtt_enb_init(int evm_id, int profile)
{
//setup_pin_mux(gpio_ddr_vtt_enb_pin_mux);
return;
}
/* setup haptics */
#define HAPTICS_MAX_FREQ 250
static void haptics_init(int evm_id, int profile)
{
//setup_pin_mux(haptics_pin_mux);
pwm_pdata[2].chan_attrib[1].max_freq = HAPTICS_MAX_FREQ;
am33xx_register_ehrpwm(2, &pwm_pdata[2]);
}
/* NAND partition information */
static struct mtd_partition am335x_nand_partitions[] = {
/* All the partition sizes are listed in terms of NAND block size */
{
.name = "SPL",
.offset = 0, /* Offset = 0x0 */
.size = SZ_128K,
},
{
.name = "SPL.backup1",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
.size = SZ_128K,
},
{
.name = "SPL.backup2",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
.size = SZ_128K,
},
{
.name = "SPL.backup3",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
.size = SZ_128K,
},
{
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
.size = 15 * SZ_128K,
},
{
.name = "U-Boot Env",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
.size = 1 * SZ_128K,
},
{
.name = "Kernel",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
.size = 40 * SZ_128K,
},
{
.name = "File System",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
.size = MTDPART_SIZ_FULL,
},
};
/* SPI 0/1 Platform Data */
/* SPI flash information */
static struct mtd_partition am335x_spi_partitions[] = {
/* All the partition sizes are listed in terms of erase size */
{
.name = "SPL",
.offset = 0, /* Offset = 0x0 */
.size = SZ_128K,
},
{
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
.size = (3 * SZ_128K) - SZ_4K,
},
{
.name = "U-Boot Env",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x7F000 */
.size = SZ_4K,
},
{
.name = "Kernel",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
.size = 866 * SZ_4K, /* size = 0x362000 */
},
{
.name = "File System",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
.size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
}
};
static const struct flash_platform_data am335x_spi_flash = {
.type = "w25q64",
.name = "spi_flash",
.parts = am335x_spi_partitions,
.nr_parts = ARRAY_SIZE(am335x_spi_partitions),
};
static struct gpmc_timings am335x_nand_timings = {
.sync_clk = 0,
.cs_on = 0,
.cs_rd_off = 44,
.cs_wr_off = 44,
.adv_on = 6,
.adv_rd_off = 34,
.adv_wr_off = 44,
.we_off = 40,
.oe_off = 54,
.access = 64,
.rd_cycle = 82,
.wr_cycle = 82,
.wr_access = 40,
.wr_data_mux_bus = 0,
};
static void evm_nand_init(int evm_id, int profile)
{
struct omap_nand_platform_data *pdata;
struct gpmc_devices_info gpmc_device[2] = {
{ NULL, 0 },
{ NULL, 0 },
};
pr_info("evm_nand_init ********************************** \n");
setup_pin_mux(nand_pin_mux);
pdata = omap_nand_init(am335x_nand_partitions,
ARRAY_SIZE(am335x_nand_partitions), 0, 0,
&am335x_nand_timings);
if (!pdata)
return;
pdata->ecc_opt =OMAP_ECC_BCH8_CODE_HW;
pdata->elm_used = true;
gpmc_device[0].pdata = pdata;
gpmc_device[0].flag = GPMC_DEVICE_NAND;
omap_init_gpmc(gpmc_device, sizeof(gpmc_device));
omap_init_elm();
}
/* TPS65217 voltage regulator support */
/* 1.8V */
static struct regulator_consumer_supply tps65217_dcdc1_consumers[] = {
{
.supply = "vdds_osc",
},
{
.supply = "vdds_pll_ddr",
},
{
.supply = "vdds_pll_mpu",
},
{
.supply = "vdds_pll_core_lcd",
},
{
.supply = "vdds_sram_mpu_bb",
},
{
.supply = "vdds_sram_core_bg",
},
{
.supply = "vdda_usb0_1p8v",
},
{
.supply = "vdds_ddr",
},
{
.supply = "vdds",
},
{
.supply = "vdds_hvx_1p8v",
},
{
.supply = "vdda_adc",
},
{
.supply = "ddr2",
},
};
/* 1.1V */
static struct regulator_consumer_supply tps65217_dcdc2_consumers[] = {
{
.supply = "vdd_mpu",
},
};
/* 1.1V */
static struct regulator_consumer_supply tps65217_dcdc3_consumers[] = {
{
.supply = "vdd_core",
},
};
/* 1.8V LDO */
static struct regulator_consumer_supply tps65217_ldo1_consumers[] = {
{
.supply = "vdds_rtc",
},
};
/* 3.3V LDO */
static struct regulator_consumer_supply tps65217_ldo2_consumers[] = {
{
.supply = "vdds_any_pn",
},
};
/* 3.3V LDO */
static struct regulator_consumer_supply tps65217_ldo3_consumers[] = {
{
.supply = "vdds_hvx_ldo3_3p3v",
},
{
.supply = "vdda_usb0_3p3v",
},
};
/* 3.3V LDO */
static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
{
.supply = "vdds_hvx_ldo4_3p3v",
},
};
/*
* FIXME: Some BeagleBones reuire a ramp_delay to settle down the set
* voltage from 0.95v to 1.25v. By default a minimum of 70msec is set
* based on experimentation. This will be removed/modified to exact
* value, once the root cause is known.
*
* The reason for extended ramp time requirement on BeagleBone is not
* known and the delay varies from board - board, if the board hangs
* with this 70msec delay then try to increase the value.
*/
static struct tps65217_rdelay dcdc2_ramp_delay = {
.ramp_delay = 70000,
};
static struct regulator_init_data tps65217_regulator_data[] = {
/* dcdc1 */
{
.constraints = {
.min_uV = 900000,
.max_uV = 1800000,
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc1_consumers),
.consumer_supplies = tps65217_dcdc1_consumers,
},
/* dcdc2 */
{
.constraints = {
.min_uV = 900000,
.max_uV = 3300000,
.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS),
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
.consumer_supplies = tps65217_dcdc2_consumers,
.driver_data = &dcdc2_ramp_delay,
.ignore_check_consumers = 1,
},
/* dcdc3 */
{
.constraints = {
.min_uV = 900000,
.max_uV = 1500000,
.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS),
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
.consumer_supplies = tps65217_dcdc3_consumers,
.ignore_check_consumers = 1,
},
/* ldo1 */
{
.constraints = {
.min_uV = 1000000,
.max_uV = 3300000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo1_consumers),
.consumer_supplies = tps65217_ldo1_consumers,
},
/* ldo2 */
{
.constraints = {
.min_uV = 900000,
.max_uV = 3300000,
.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS),
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo2_consumers),
.consumer_supplies = tps65217_ldo2_consumers,
},
/* ldo3 */
{
.constraints = {
.min_uV = 1800000,
.max_uV = 3300000,
.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS),
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo3_consumers),
.consumer_supplies = tps65217_ldo3_consumers,
},
/* ldo4 */
{
.constraints = {
.min_uV = 1800000,
.max_uV = 3300000,
.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS),
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo4_consumers),
.consumer_supplies = tps65217_ldo4_consumers,
},
};
static struct tps65217_board beaglebone_tps65217_info = {
.tps65217_init_data = &tps65217_regulator_data[0],
.status_off = true,
};
static struct i2c_board_info am335x_i2c1_boardinfo[] = {
#if 0
{
I2C_BOARD_INFO("tlv320aic3x", 0x1b),
},
{
I2C_BOARD_INFO("tsl2550", 0x39),
},
{
I2C_BOARD_INFO("tmp275", 0x48),
},
#endif
};
static void i2c1_init(int evm_id, int profile)
{
//setup_pin_mux(i2c1_pin_mux);
omap_register_i2c_bus(2, 100, am335x_i2c1_boardinfo,
ARRAY_SIZE(am335x_i2c1_boardinfo));
return;
}
static struct i2c_board_info am335x_i2c2_boardinfo[] = {
};
static void i2c2_init(int evm_id, int profile)
{
//setup_pin_mux(i2c2_pin_mux);
omap_register_i2c_bus(3, 100, am335x_i2c2_boardinfo,
ARRAY_SIZE(am335x_i2c2_boardinfo));
return;
}
/* Setup McASP 1 */
static void mcasp1_init(int evm_id, int profile)
{
pr_info("--------mcasp1_init\n");
/* Configure McASP */
setup_pin_mux(mcasp1_pin_mux);
switch (evm_id) {
case EVM_SK:
pr_info("--------evm_id is SK\n");
am335x_register_mcasp(&am335x_evm_sk_snd_data1,1);
break;
default:
am335x_register_mcasp(&am335x_evm_snd_data1,1);
}
return;
}
static void mmc1_init(int evm_id, int profile)
{
/*setup_pin_mux(mmc1_common_pin_mux);
setup_pin_mux(mmc1_dat4_7_pin_mux);
setup_pin_mux(mmc1_wp_only_pin_mux);
setup_pin_mux(mmc1_cd_only_pin_mux);
am335x_mmc[1].mmc = 2;
am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
am335x_mmc[1].gpio_cd = GPIO_TO_PIN(1, 28);//--czx
am335x_mmc[1].gpio_wp = -EINVAL;//GPIO_TO_PIN(1, 29);
am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
/* mmc will be initialized when mmc0_init is called */
return;
}
static void mmc1_wl12xx_init(int evm_id, int profile)
{
/*setup_pin_mux(mmc1_common_pin_mux);
am335x_mmc[1].mmc = 2;
am335x_mmc[1].name = "wl1271";
am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD;
am335x_mmc[1].nonremovable = true;
am335x_mmc[1].pm_caps = MMC_PM_KEEP_POWER;
am335x_mmc[1].gpio_cd = -EINVAL;
am335x_mmc[1].gpio_wp = -EINVAL;
am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
}
static void mmc1_emmc_init(int evm_id, int profile)
{
/*setup_pin_mux(mmc1_common_pin_mux);
setup_pin_mux(mmc1_dat4_7_pin_mux);
am335x_mmc[1].mmc = 2;
am335x_mmc[1].caps = MMC_CAP_8_BIT_DATA;
am335x_mmc[1].gpio_cd = -EINVAL;
am335x_mmc[1].gpio_wp = -EINVAL;
am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
/* mmc will be initialized when mmc0_init is called */
return;
}
static void mmc2_wl12xx_init(int evm_id, int profile)
{
/*setup_pin_mux(mmc2_wl12xx_pin_mux);
am335x_mmc[1].mmc = 3;
am335x_mmc[1].name = "wl1271";
am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD;
am335x_mmc[1].nonremovable = true;
am335x_mmc[1].gpio_cd = -EINVAL;
am335x_mmc[1].gpio_wp = -EINVAL;
am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
/* mmc will be initialized when mmc0_init is called */
return;
}
static void uart1_wl12xx_init(int evm_id, int profile)
{
setup_pin_mux(uart1_wl12xx_pin_mux);
}
static void wl12xx_bluetooth_enable(void)
{
int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
"bt_en\n");
if (status < 0)
pr_err("Failed to request gpio for bt_enable");
pr_info("Configure Bluetooth Enable pin...\n");
gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
}
#define AM33XX_CTRL_REGADDR(reg) \
AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
/* wlan enable pin */
#define AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET 0x087C
static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
{
int pad_mux_value;
if (on) {
gpio_direction_output(am335xevm_wlan_data.wlan_enable_gpio, 1);
/* Enable pullup on the WLAN enable pin for keeping wlan active during suspend
in wowlan mode */
if ( am335x_evm_get_id() == EVM_SK ) {
pad_mux_value = readl(AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
pad_mux_value &= (~AM33XX_PULL_DISA);
writel(pad_mux_value, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
}
mdelay(70);
} else {
gpio_direction_output(am335xevm_wlan_data.wlan_enable_gpio, 0);
/* Disable pullup on the WLAN enable when WLAN is off */
if ( am335x_evm_get_id() == EVM_SK ) {
pad_mux_value = readl(AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
pad_mux_value |= AM33XX_PULL_DISA;
writel(pad_mux_value, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
}
}
return 0;
}
static void d_can_init(int evm_id, int profile)
{
switch (evm_id) {
case IND_AUT_MTR_EVM:
if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
setup_pin_mux(d_can_gp_pin_mux);
/* Instance Zero */
am33xx_d_can_init(0);
}
break;
case GEN_PURP_EVM:
case GEN_PURP_DDR3_EVM:
if (profile == PROFILE_1) {
setup_pin_mux(d_can_gp_pin_mux);
/* Instance One */
am33xx_d_can_init(1);
}
break;
default:
break;
}
}
static void mmc0_init(int evm_id, int profile)
{
switch (evm_id) {
case BEAGLE_BONE_A3:
case BEAGLE_BONE_OLD:
case EVM_SK:
setup_pin_mux(mmc0_common_pin_mux);
//setup_pin_mux(mmc0_cd_only_pin_mux);
break;
default:
setup_pin_mux(mmc0_common_pin_mux);
//setup_pin_mux(mmc0_cd_only_pin_mux);
break;
}
omap2_hsmmc_init(am335x_mmc);
return;
}
static struct i2c_board_info tps65217_i2c_boardinfo[] = {
{
I2C_BOARD_INFO("tps65217", TPS65217_I2C_ID),
.platform_data = &beaglebone_tps65217_info,
},
};
static void tps65217_init(int evm_id, int profile)
{
struct i2c_adapter *adapter;
struct i2c_client *client;
struct device *mpu_dev;
struct tps65217 *tps;
unsigned int val;
int ret;
mpu_dev = omap_device_get_by_hwmod_name("mpu");
if (!mpu_dev)
pr_warning("%s: unable to get the mpu device\n", __func__);
/* I2C1 adapter request */
adapter = i2c_get_adapter(1);
if (!adapter) {
pr_err("failed to get adapter i2c1\n");
return;
}
client = i2c_new_device(adapter, tps65217_i2c_boardinfo);
if (!client)
pr_err("failed to register tps65217 to i2c1\n");
i2c_put_adapter(adapter);
tps = (struct tps65217 *)i2c_get_clientdata(client);
ret = tps65217_reg_read(tps, TPS65217_REG_STATUS, &val);
if (ret) {
pr_err("failed to read tps65217 status reg\n");
return;
}
if (!(val & TPS65217_STATUS_ACPWR)) {
/* If powered by USB then disable OPP120 and OPPTURBO */
pr_info("Maximum current provided by the USB port is 500mA"
" which is not sufficient\nwhen operating @OPP120 and"
" OPPTURBO. The current requirement for some\nuse-cases"
" using OPP100 might also exceed the maximum current"
" that the\nUSB port can provide. Unless you are fully"
" confident that the current\nrequirements for OPP100"
" use-case don't exceed the USB limits, switching\nto"
" AC power is recommended.\n");
opp_disable(mpu_dev, 600000000);
opp_disable(mpu_dev, 720000000);
}
}
static void mmc0_no_cd_init(int evm_id, int profile)
{
setup_pin_mux(mmc0_common_pin_mux);
omap2_hsmmc_init(am335x_mmc);
return;
}
/* Configure GPIOs for GPIO Keys */
static struct gpio_keys_button am335x_evm_gpio_buttons[] = {
{ //K1 --czx
.code = BTN_0,
.gpio = GPIO_TO_PIN(3, 14),
.desc = "SW1",
},
{ //K2
.code = BTN_1,
.gpio = GPIO_TO_PIN(3, 15),
.desc = "SW2",
},
{ //K3
.code = BTN_2,
.gpio = GPIO_TO_PIN(3, 16),
.desc = "SW3",
.wakeup = 1,
},
{ //K4
.code = BTN_3,
.gpio = GPIO_TO_PIN(3, 18),
.desc = "SW4",
},
};
static struct gpio_keys_platform_data am335x_evm_gpio_key_info = {
.buttons = am335x_evm_gpio_buttons,
.nbuttons = ARRAY_SIZE(am335x_evm_gpio_buttons),
};
static struct platform_device am335x_evm_gpio_keys = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &am335x_evm_gpio_key_info,
},
};
static void gpio_keys_init(int evm_id, int profile)
{
int err;
pr_info("gpio_keys_init ********************************** \n");
setup_pin_mux(gpio_keys_pin_mux);
err = platform_device_register(&am335x_evm_gpio_keys);
if (err)
pr_err("failed to register gpio key device\n");
}
static struct gpio_led gpio_leds[] = {
{
.name = "am335x:EVM_SK:usr0",
.gpio = GPIO_TO_PIN(1, 30), /* D1 */ //--czx
},
{
.name = "am335x:EVM_SK:usr1",
.gpio = GPIO_TO_PIN(1, 31), /* D2 */ //--czx
.default_trigger = "heartbeat",
},
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_led_info,
},
};
static void gpio_led_init(int evm_id, int profile)
{
int err;
pr_info("gpio_led_init ********************************** \n");
setup_pin_mux(gpio_led_mux);
err = platform_device_register(&leds_gpio);
if (err)
pr_err("failed to register gpio led device\n");
}
static void profibus_init(int evm_id, int profile)
{
//setup_pin_mux(profibus_pin_mux);
return;
}
static struct omap_rtc_pdata am335x_rtc_info = {
.pm_off = false,
.wakeup_capable = 0,
};
static void am335x_rtc_init(int evm_id, int profile)
{
void __iomem *base;
struct clk *clk;
struct omap_hwmod *oh;
struct platform_device *pdev;
char *dev_name = "am33xx-rtc";
clk = clk_get(NULL, "rtc_fck");
if (IS_ERR(clk)) {
pr_err("rtc : Failed to get RTC clock\n");
return;
}
if (clk_enable(clk)) {
pr_err("rtc: Clock Enable Failed\n");
return;
}
base = ioremap(AM33XX_RTC_BASE, SZ_4K);
if (WARN_ON(!base))
return;
/* Unlock the rtc's registers */
writel(0x83e70b13, base + 0x6c);
writel(0x95a4f1e0, base + 0x70);
/*
* Enable the 32K OSc
* TODO: Need a better way to handle this
* Since we want the clock to be running before mmc init
* we need to do it before the rtc probe happens
*/
writel(0x48, base + 0x54);
iounmap(base);
switch (evm_id) {
case BEAGLE_BONE_A3:
case BEAGLE_BONE_OLD:
am335x_rtc_info.pm_off = true;
break;
default:
break;
}
clk_disable(clk);
clk_put(clk);
if (omap_rev() >= AM335X_REV_ES2_0)
am335x_rtc_info.wakeup_capable = 1;
oh = omap_hwmod_lookup("rtc");
if (!oh) {
pr_err("could not look up %s\n", "rtc");
return;
}
pdev = omap_device_build(dev_name, -1, oh, &am335x_rtc_info,
sizeof(struct omap_rtc_pdata), NULL, 0, 0);
WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
dev_name, oh->name);
}
/* Enable clkout2 */
static struct pinmux_config clkout2_pin_mux[] = {
//{"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
{NULL, 0},
};
static void clkout2_enable(int evm_id, int profile)
{
struct clk *ck_32;
ck_32 = clk_get(NULL, "clkout2_ck");
if (IS_ERR(ck_32)) {
pr_err("Cannot clk_get ck_32\n");
return;
}
clk_enable(ck_32);
setup_pin_mux(clkout2_pin_mux);
}
static void sgx_init(int evm_id, int profile)
{
if (omap3_has_sgx()) {
am33xx_gpu_init();
}
}
/* General Purpose EVM */
/*static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
{am335x_rtc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{clkout2_enable, DEV_ON_BASEBOARD, PROFILE_ALL},
{enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
PROFILE_2 | PROFILE_7) },
{lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
PROFILE_2 | PROFILE_7) },
{mfd_tscadc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
PROFILE_2 | PROFILE_7) },
{rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
PROFILE_4 | PROFILE_6) },
{usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{evm_nand_init, DEV_ON_DGHTR_BRD,
(PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
{i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
{lis331dlh_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
{mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
{mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
{mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
PROFILE_5)},
{mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
{mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
{spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
{uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
PROFILE_5)},
{wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
{d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
{matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
{volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
{uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
{haptics_init, DEV_ON_DGHTR_BRD, (PROFILE_4)},
{sgx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{NULL, 0, 0},
};
*/
/* EVM - Starter Kit */
static struct evm_dev_cfg evm_sk_dev_cfg[] = {
{am335x_rtc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{evm_nand_init, DEV_ON_BASEBOARD, PROFILE_ALL},//--czx
//{spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},//--czx
{usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},//--czx
{usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},//--czx
{mmc0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
//{mmc1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{rgmii2_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{lcdc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{enable_ecap0, DEV_ON_BASEBOARD, PROFILE_ALL},//--lh
{mfd_tscadc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{gpio_keys_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{gpio_led_init, DEV_ON_BASEBOARD, PROFILE_ALL},
//{lis331dlh_init, DEV_ON_BASEBOARD, PROFILE_ALL}, //--lh
{mcasp1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{uart4_init, DEV_ON_BASEBOARD, PROFILE_ALL},
// {uart1_wl12xx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
// {wl12xx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
//{gpio_ddr_vtt_enb_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{sgx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{NULL, 0, 0},
};
static int am33xx_evm_tx_clk_dly_phy_fixup(struct phy_device *phydev)
{
phy_write(phydev, AR8051_PHY_DEBUG_ADDR_REG,
AR8051_DEBUG_RGMII_CLK_DLY_REG);
phy_write(phydev, AR8051_PHY_DEBUG_DATA_REG, AR8051_RGMII_TX_CLK_DLY);
return 0;
}
#define AM33XX_VDD_CORE_OPP50_UV 1100000
#define AM33XX_OPP120_FREQ 600000000
#define AM33XX_OPPTURBO_FREQ 720000000
#define AM33XX_ES2_0_VDD_CORE_OPP50_UV 950000
#define AM33XX_ES2_0_OPP120_FREQ 720000000
#define AM33XX_ES2_0_OPPTURBO_FREQ 800000000
#define AM33XX_ES2_0_OPPNITRO_FREQ 1000000000
#define AM33XX_ES2_1_VDD_CORE_OPP50_UV 950000
#define AM33XX_ES2_1_OPP120_FREQ 720000000
#define AM33XX_ES2_1_OPPTURBO_FREQ 800000000
#define AM33XX_ES2_1_OPPNITRO_FREQ 1000000000
static void am335x_opp_update(void)
{
u32 rev;
int voltage_uv = 0;
struct device *core_dev, *mpu_dev;
struct regulator *core_reg;
core_dev = omap_device_get_by_hwmod_name("l3_main");
mpu_dev = omap_device_get_by_hwmod_name("mpu");
if (!mpu_dev || !core_dev) {
pr_err("%s: Aiee.. no mpu/core devices? %p %p\n", __func__,
mpu_dev, core_dev);
return;
}
core_reg = regulator_get(core_dev, "vdd_core");
if (IS_ERR(core_reg)) {
pr_err("%s: unable to get core regulator\n", __func__);
return;
}
/*
* Ensure physical regulator is present.
* (e.g. could be dummy regulator.)
*/
voltage_uv = regulator_get_voltage(core_reg);
if (voltage_uv < 0) {
pr_err("%s: physical regulator not present for core" \
"(%d)\n", __func__, voltage_uv);
regulator_put(core_reg);
return;
}
pr_debug("%s: core regulator value %d\n", __func__, voltage_uv);
if (voltage_uv > 0) {
rev = omap_rev();
switch (rev) {
case AM335X_REV_ES1_0:
if (voltage_uv <= AM33XX_VDD_CORE_OPP50_UV) {
/*
* disable the higher freqs - we dont care about
* the results
*/
opp_disable(mpu_dev, AM33XX_OPP120_FREQ);
opp_disable(mpu_dev, AM33XX_OPPTURBO_FREQ);
}
break;
case AM335X_REV_ES2_0:
if (voltage_uv <= AM33XX_ES2_0_VDD_CORE_OPP50_UV) {
/*
* disable the higher freqs - we dont care about
* the results
*/
opp_disable(mpu_dev,
AM33XX_ES2_0_OPP120_FREQ);
opp_disable(mpu_dev,
AM33XX_ES2_0_OPPTURBO_FREQ);
opp_disable(mpu_dev,
AM33XX_ES2_0_OPPNITRO_FREQ);
}
break;
case AM335X_REV_ES2_1:
/* FALLTHROUGH */
default:
if (voltage_uv <= AM33XX_ES2_1_VDD_CORE_OPP50_UV) {
/*
* disable the higher freqs - we dont care about
* the results
*/
opp_disable(mpu_dev,
AM33XX_ES2_1_OPP120_FREQ);
opp_disable(mpu_dev,
AM33XX_ES2_1_OPPTURBO_FREQ);
opp_disable(mpu_dev,
AM33XX_ES2_1_OPPNITRO_FREQ);
}
break;
}
}
}
/*
static void setup_general_purpose_evm(void)
{
u32 prof_sel = am335x_get_profile_selection();
u32 boardid = GEN_PURP_EVM;
pr_info("setup_general_purpose_evm ********************************** \n");
if (!strncmp("1.5A", config.version, 4))
boardid = GEN_PURP_DDR3_EVM;
pr_info("The board is general purpose EVM %sin profile %d\n",
((boardid == GEN_PURP_DDR3_EVM) ? "with DDR3 " : ""),
prof_sel);
_configure_device(boardid, gen_purp_evm_dev_cfg, (1L << prof_sel));
am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, NULL);
/* Atheros Tx Clk delay Phy fixup */
/*phy_register_fixup_for_uid(AM335X_EVM_PHY_ID, AM335X_EVM_PHY_MASK,
am33xx_evm_tx_clk_dly_phy_fixup);
}
*/
/* EVM - Starter Kit */
static void setup_starterkit(void)
{
pr_info("The board is a AM335x Starter Kit.\n");
/* Starter Kit has Micro-SD slot which doesn't have Write Protect pin */
am335x_mmc[0].gpio_wp = -EINVAL;
_configure_device(EVM_SK, evm_sk_dev_cfg, PROFILE_NONE);
am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, NULL);
/* Atheros Tx Clk delay Phy fixup */
phy_register_fixup_for_uid(AM335X_EVM_PHY_ID, AM335X_EVM_PHY_MASK,
am33xx_evm_tx_clk_dly_phy_fixup);
}
static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
{
int ret;
/*
* Read from the EEPROM to see the presence of daughter board.
* If present, print the cpld version.
*/
ret = m->read(m, (char *)&config1, 0, sizeof(config1));
if (ret == sizeof(config1)) {
pr_info("Detected a daughter card on AM335x EVM..");
daughter_brd_detected = true;
}
else {
pr_info("No daughter card found\n");
daughter_brd_detected = false;
return;
}
if (!strncmp("CPLD", config1.cpld_ver, 4))
pr_info("CPLD version: %s\n", config1.cpld_ver);
else
pr_err("Unknown CPLD version found\n");
}
static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
{
int ret;
char tmp[10];
pr_info("am335x_evm_setup ********************************** \n");
/* 1st get the MAC address from EEPROM */
am335x_mac_addr[0][0] = 0x00;
am335x_mac_addr[0][1] = 0x22;
am335x_mac_addr[0][2] = 0x15;
am335x_mac_addr[0][3] = 0x00;
am335x_mac_addr[0][4] = 0x00;
am335x_mac_addr[0][5] = 0x01;
am335x_mac_addr[1][0] = 0x00;
am335x_mac_addr[1][1] = 0x22;
am335x_mac_addr[1][2] = 0x15;
am335x_mac_addr[1][3] = 0x00;
am335x_mac_addr[1][4] = 0x00;
am335x_mac_addr[1][5] = 0x02;
am335x_mac_addr[2][0] = 0x00;
am335x_mac_addr[2][1] = 0x22;
am335x_mac_addr[2][2] = 0x15;
am335x_mac_addr[2][3] = 0x00;
am335x_mac_addr[2][4] = 0x00;
am335x_mac_addr[2][5] = 0x02;
/* Fillup global mac id */
am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
&am335x_mac_addr[1][0]);
config.header = 0xEE3355AA;
memcpy(config.name,"A335X_SK",8);
memcpy(config.version,"V1.0",4);
memcpy(config.opt,"SKU#01",6);
snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
pr_info("Board name: %s\n", tmp);
snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
pr_info("Board version: %s\n", tmp);
daughter_brd_detected = false;
setup_starterkit();
am335x_opp_update();
/*
* For now, Beaglebone Black uses PG 2.0 that are speed binned and operate
* up to 1GHz. So re-enable Turbo and Nitro modes,
*/
if (!strncmp("A335BNLT", config.name, 8)) {
struct device *mpu_dev;
mpu_dev = omap_device_get_by_hwmod_name("mpu");
opp_enable(mpu_dev,
AM33XX_ES2_0_OPPTURBO_FREQ);
opp_enable(mpu_dev,
AM33XX_ES2_0_OPPNITRO_FREQ);
}
/* SmartReflex also requires board information. */
am33xx_sr_init();
return;
out:
/*
* If the EEPROM hasn't been programed or an incorrect header
* or board name are read then the hardware details are unknown.
* Notify the user and call machine_halt to stop the boot process.
*/
pr_err("The error message above indicates that there is an issue with\n"
"the EEPROM or the EEPROM contents. After verifying the EEPROM\n"
"contents, if any, refer to the %s function in the\n"
"%s file to modify the board\n"
"initialization code to match the hardware configuration\n",
__func__ , __FILE__);
machine_halt();
}
static struct at24_platform_data am335x_daughter_board_eeprom_info = {
.byte_len = (256*1024) / 8,
.page_size = 64,
.flags = AT24_FLAG_ADDR16,
.setup = am335x_setup_daughter_board,
.context = (void *)NULL,
};
static struct at24_platform_data am335x_baseboard_eeprom_info = {
.byte_len = (256*1024) / 8,
.page_size = 64,
.flags = AT24_FLAG_ADDR16,
.setup = am335x_evm_setup,
.context = (void *)NULL,
};
static struct regulator_init_data am335x_dummy = {
.constraints.always_on = true,
};
static struct regulator_consumer_supply am335x_vdd1_supply[] = {
REGULATOR_SUPPLY("vdd_mpu", NULL),
};
static struct regulator_init_data am335x_vdd1 = {
.constraints = {
.min_uV = 600000,
.max_uV = 1500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
.consumer_supplies = am335x_vdd1_supply,
.ignore_check_consumers = 1,
};
static struct regulator_consumer_supply am335x_vdd2_supply[] = {
REGULATOR_SUPPLY("vdd_core", NULL),
};
static struct regulator_init_data am335x_vdd2 = {
.constraints = {
.min_uV = 600000,
.max_uV = 1500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(am335x_vdd2_supply),
.consumer_supplies = am335x_vdd2_supply,
.ignore_check_consumers = 1,
};
static struct tps65910_board am335x_tps65910_info = {
.tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1,
.tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_vdd2,
.tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy,
.tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy,
};
/*
* Daughter board Detection.
* Every board has a ID memory (EEPROM) on board. We probe these devices at
* machine init, starting from daughter board and ending with baseboard.
* Assumptions :
* 1. probe for i2c devices are called in the order they are included in
* the below struct. Daughter boards eeprom are probed 1st. Baseboard
* eeprom probe is called last.
*/
static struct i2c_board_info __initdata am335x_i2c0_boardinfo[] = {
#if 1
{
/* Daughter Board EEPROM */
I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
.platform_data = &am335x_daughter_board_eeprom_info,
},
{
/* Baseboard board EEPROM */
I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
.platform_data = &am335x_baseboard_eeprom_info,
},
#endif
/*{
I2C_BOARD_INFO("cpld_reg", 0x35),
},*/
{
I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
.platform_data = &am335x_tps65910_info,
},
{
I2C_BOARD_INFO("sgtl5000", 0x0A),
},
};
static struct omap_musb_board_data musb_board_data = {
.interface_type = MUSB_INTERFACE_ULPI,
/*
* mode[0:3] = USB0PORT's mode
* mode[4:7] = USB1PORT's mode
* AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
*/
.mode = (MUSB_HOST << 4) | MUSB_OTG,
.power = 500,
.instances = 1,
};
static int cpld_reg_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
cpld_client = client;
return 0;
}
static int __devexit cpld_reg_remove(struct i2c_client *client)
{
cpld_client = NULL;
return 0;
}
static const struct i2c_device_id cpld_reg_id[] = {
{ "cpld_reg", 0 },
{ }
};
static struct i2c_driver cpld_reg_driver = {
.driver = {
.name = "cpld_reg",
},
.probe = cpld_reg_probe,
.remove = cpld_reg_remove,
.id_table = cpld_reg_id,
};
static void evm_init_cpld(void)
{
i2c_add_driver(&cpld_reg_driver);
}
static void __init am335x_evm_i2c_init(void)
{
/* Initially assume General Purpose EVM Config */
am335x_evm_id = GEN_PURP_EVM;
setup_pin_mux(i2c0_pin_mux);
//evm_init_cpld();
omap_register_i2c_bus(1, 100, am335x_i2c0_boardinfo,
ARRAY_SIZE(am335x_i2c0_boardinfo));
}
void __iomem *am33xx_emif_base;
void __iomem * __init am33xx_get_mem_ctlr(void)
{
am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
if (!am33xx_emif_base)
pr_warning("%s: Unable to map DDR2 controller", __func__);
return am33xx_emif_base;
}
void __iomem *am33xx_get_ram_base(void)
{
return am33xx_emif_base;
}
void __iomem *am33xx_gpio0_base;
void __iomem *am33xx_get_gpio0_base(void)
{
am33xx_gpio0_base = ioremap(AM33XX_GPIO0_BASE, SZ_4K);
return am33xx_gpio0_base;
}
static struct resource am33xx_cpuidle_resources[] = {
{
.start = AM33XX_EMIF0_BASE,
.end = AM33XX_EMIF0_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
};
/* AM33XX devices support DDR2 power down */
static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
.ddr2_pdown = 1,
};
static struct platform_device am33xx_cpuidle_device = {
.name = "cpuidle-am33xx",
.num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
.resource = am33xx_cpuidle_resources,
.dev = {
.platform_data = &am33xx_cpuidle_pdata,
},
};
static void __init am33xx_cpuidle_init(void)
{
int ret;
am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
ret = platform_device_register(&am33xx_cpuidle_device);
if (ret)
pr_warning("AM33XX cpuidle registration failed\n");
}
static void __init am335x_evm_init(void)
{
am33xx_cpuidle_init();
am33xx_mux_init(board_mux);
omap_serial_init();
am335x_evm_i2c_init();
omap_sdrc_init(NULL, NULL);
usb_musb_init(&musb_board_data);
omap_board_config = am335x_evm_config;
omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
/* Create an alias for icss clock */
if (clk_add_alias("pruss", NULL, "pruss_uart_gclk", NULL))
pr_warn("failed to create an alias: icss_uart_gclk --> pruss\n");
/* Create an alias for gfx/sgx clock */
if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
pr_warn("failed to create an alias: gfx_fclk --> sgx_ck\n");
}
static void __init am335x_evm_map_io(void)
{
omap2_set_globals_am33xx();
omapam33xx_map_common_io();
}
MACHINE_START(AM335XEVM, "am335xevm")
/* Maintainer: Texas Instruments */
.atag_offset = 0x100,
.map_io = am335x_evm_map_io,
.init_early = am33xx_init_early,
.init_irq = ti81xx_init_irq,
.handle_irq = omap3_intc_handle_irq,
.timer = &omap3_am33xx_timer,
.init_machine = am335x_evm_init,
MACHINE_END
MACHINE_START(AM335XIAEVM, "am335xiaevm")
/* Maintainer: Texas Instruments */
.atag_offset = 0x100,
.map_io = am335x_evm_map_io,
.init_irq = ti81xx_init_irq,
.init_early = am33xx_init_early,
.timer = &omap3_am33xx_timer,
.init_machine = am335x_evm_init,
MACHINE_END
我也遇到了和你差不多的问题，不过我是两个EHT都无法PING通，使用的是AR8035，使用RGMII接口和英蓓特 SBC8600B是一样的，但是网络能LINK UP，LINK DOWN，也能从LINUX下看到有TX,RX的数据，但就是PING不通，所有可能的原因都查了好几遍还是无果。说明如下：
1、使用的接口为RGMII，在10M,100M下都进行过测试，10M下MII信号波型较好，100M就很差了，但是另一个使用RTL8211E的开发板也是这样的波型，应当可以排除由于信号电平不足引起。
2、开始怀疑时序上问题，因为RGMII使用了时钟的双边延对数据进行取样，RGMII一般也带内部的delay,配置内部延时无效，通过外部将CLK延时无效（能够看到建立时间比更改前要长了，最后测试无效。
3、AR8035支持三种的debug模式，分别是 Digital Loopback，External cable loopback，Remote PHY Loopback，这三种都是通过配置寄存器方式测试，但是文档上没有提到任何如何获知当前测试结果的说明，第一、二配了后无效，第三有一个寄存器位无法写入。最后无果。
4、其它还有怀疑MAC地址，芯片的硬件ID等，都无果。
如果你已经解决，也请告知，谢谢。
你好！
不知道你们的问题是否已经解决，我的电路板上使用了AM3352 + AR8031芯片，发现网络不通。
我通过飞线将AM3352连接到之前用过的PHY芯片RTL8211EG上面，网络可以正常通讯。所以推断问题在AR8031上面，我使用的也是RGMII接口，使用ping命令，系统一直提示网络连接未就绪，测试发现网络的差分对上无任何波形，但AR8031已经工作。
