C5000 MCBSP SPI

void Init_McBSP(void)
{
//----------------------------
// McBSP0
//----------------------------
U16 i;
U8 data;
U16 regSPCR1=0;
U16 regSPCR2=0;
U16 regPCR=0;

//======== Clear the transmitter/receiver reset bit
//======== Clear the sample rate generator reset bit
DSP_IOREG_WRITE(SPCR10,regSPCR1);//RRST=0,
DSP_IOREG_WRITE(SPCR20,regSPCR2);//XRST=0,GRST=0,

//======== configure the McBSP for an SPI master
regSPCR1=0x1000;//bit12:11=10 CLKSTP = 10b Clock stop mode enabled, without clock delay
DSP_IOREG_WRITE(SPCR10,regSPCR1);

//Bit0 CLKRP=0,
//Bit1 CLKXP=0,
//Bit3 FSXP=1
//Bit7 SCLKME=0,
//Bit9 CLKXM=1,
//Bit11 FSXM =1
regPCR=BIT11|CLKXM|BIT3;
DSP_IOREG_WRITE(PCR0,regPCR );

//Bit12 FSGM=0
//Bit13 CLKSM=1;
DSP_IOREG_WRITE(SRGR20,BIT13);

DSP_IOREG_WRITE(SRGR10, 2);//Bit7:0 CLKGDV =75M/3=25M

DSP_IOREG_WRITE(XCR20,1);//Bit1:0 XDATDLY =01b ;
DSP_IOREG_WRITE(RCR20,1);//Bit1:0 RDATDLY =01b ;

//======== Enable sample rate generator

regSPCR2=BIT6;//GRST=1;
DSP_IOREG_WRITE(SPCR20,regSPCR2);
for(i=0;i<600;i++){}

//======== Enable transmitter and receiver
regSPCR2|=BIT0;//Bit0 XRST=1
DSP_IOREG_WRITE(SPCR20,regSPCR2);

regSPCR1|=BIT0;//Bit0 RRST=1
DSP_IOREG_WRITE(SPCR10,regSPCR1);

//======== Enable frame sync generator
regSPCR2|=BIT7;//Bit7 FRST
DSP_IOREG_WRITE(SPCR20,regSPCR2);
for(i=0;i<600;i++){}

while(1)
{
// if(DSP_IOREG_READ(SPCR20)&BIT1)//Bit1 XRDY=1 Transmitter ready: DXR[1,2] is ready to accept new data.
{
// DSP_IOREG_WRITE(DXR10,0xF0);
}
if(DSP_IOREG_READ(SPCR10)&BIT1)//Bit1 RRDY=1 Receiver ready: New data can be read from DRR[1,2].
{
data=DSP_IOREG_READ(DRR10);
}

}