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6678与Xilinx Virtex6FPGA间高速串行SRIO通信,实现4通道3.125Gbps数据传输

哪位大神就上面的题目提出点指导意见,大学生一枚,毕设做这个,但之前接触不多,毫无思绪。或者推荐点文档和资料,非常感谢!

  • 硬件设计参考EVM设计:http://www.deyisupport.com/question_answer/dsp_arm/c6000_multicore/f/53/t/51760.aspx

    DSP侧SRIO软件的配置参考MCSDK及STK: http://www.deyisupport.com/question_answer/dsp_arm/c6000_multicore/f/53/t/47664.aspx

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