If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
/* DDR_SDTIM2 = 0x30b37FE3; */ TEMP = 0; TEMP |= 0x3 << 28; // T_XP bit field 30:28 TEMP |= 0xb3 << 16; // T_XSNR bit field 24:16 TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6 TEMP |= 0x4 << 3; // T_RTP bit field 5:3 TEMP |= 0x3; // T_CKE bit field 2:0 DDR_SDTIM2 = TEMP;
3：DDR_SDTIM3部分
/* DDR_SDTIM3 = 0x559F8adF; */ TEMP = 0; TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value) TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value) TEMP |= 0x4 << 21; // T_CKESR bit field 23:21 TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15 TEMP |= 0xad << 4; // T_RFC bit field 12:4 TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value) DDR_SDTIM3 = TEMP;
4：DDR_SDCFG部分
/* DDR_SDCFG = 0x63062b32; */ /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32; // last config write DRAM init occurs */ TEMP = 0; TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value) TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27 TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24 TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21 TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18 TEMP |= 0x2 << 16; // CWL bit field 17:16 TEMP |= 0x0 << 14; // NM bit field 15:14 TEMP |= 0xA << 10; // CL bit field 13:10 TEMP |= 0x6 << 7; // ROWSIZE bit field 9:7 TEMP |= 0x3 << 4; // IBANK bit field 6:4 TEMP |= 0x0 << 3; // EBANK bit field 3:3 TEMP |= 0x2; // PAGESIZE bit field 2:0 DDR_SDCFG = TEMP;
/* Wake up EMIF16 module:*/ /* program pdctl and mdctl to enable the module. */ CSL_PSC_enablePowerDomain(power_domain_num); CSL_PSC_setModuleNextState (mdctl_emif16_module_num, PSC_MODSTATE_ENABLE);
// start the process and wait. but timeout in 1000 loops. CSL_PSC_startStateTransition(power_domain_num); /* Wait until the state transition process is completed. */ while (!CSL_PSC_isStateTransitionDone ( power_domain_num));
/* Return PSC status */ if ((CSL_PSC_getPowerDomainState( power_domain_num) == PSC_PDSTATE_ON) && (CSL_PSC_getModuleState (mdctl_emif16_module_num) == PSC_MODSTATE_ENABLE)) { /*Ready for use */ printf("EMIF16 PSC success\n");; } else { /*Return error */ printf("EMIF16 PSC fail\n"); }
