This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Dtimer無法輸出pwm

Other Parts Discussed in Thread: AM3354

            目前使用的是am3354(ZCZ)
            目的是使E18這隻腳輸出PWM波形
            做法是配置E18為timer7, 並設定DTTIMER7相關參數
            但目前輸出都沒有變化, 不曉得是否少了哪些步驟?
            
            參考20.1.3.5 Pulse-Width Modulation後的詳細做法如下:
            // Initialize the ARM Interrupt Controller.
            IntAINTCInit();
            
            #define TIMER_INITIAL_COUNT             (0xFFFF0000u)
            #define TIMER_RLD_COUNT                 (0xFFFF0000u)
            
            // -----Pinmux-----
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_CTSN(0)) = ((0x00000020u) + CONTROL_CONF_MUXMODE(5));
            // -----Timer CLK-----
            DMTimer7ModuleClkConfig();
            // -----IRQ-----
            IntMasterIRQEnable();
            IntRegister(SYS_INT_TINT7, DMTimer7Isr);
            IntPrioritySet(SYS_INT_TINT7, 10, AINTC_HOSTINT_ROUTE_IRQ);
            IntSystemEnable(SYS_INT_TINT7);
            // -----Timer Counting Rate-----
            DMTimerCounterSet(SOC_DMTIMER_7_REGS, TIMER_INITIAL_COUNT);
            DMTimerReloadSet(SOC_DMTIMER_7_REGS, TIMER_RLD_COUNT);
            DMTimerModeConfigure(SOC_DMTIMER_7_REGS, DMTIMER_AUTORLD_NOCMP_ENABLE);
            // -----Trigger output mode-----
            DMTimerWaitForWrite(DMTIMER_WRITE_POST_TCLR, SOC_DMTIMER_7_REGS);
            HWREG(SOC_DMTIMER_7_REGS + DMTIMER_TCLR) &= ~DMTIMER_TCLR_TRG;
            DMTimerWaitForWrite(DMTIMER_WRITE_POST_TCLR, SOC_DMTIMER_7_REGS);
            HWREG(SOC_DMTIMER_7_REGS + DMTIMER_TCLR) |= (DMTIMER_TCLR_TRG_OVERFLOWANDMATCH << DMTIMER_TCLR_TRG_SHIFT);
            // -----plus or toggle-----
            DMTimerWaitForWrite(DMTIMER_WRITE_POST_TCLR, SOC_DMTIMER_7_REGS);
            HWREG(SOC_DMTIMER_7_REGS + DMTIMER_TCLR) &= ~DMTIMER_TCLR_PT;
            DMTimerWaitForWrite(DMTIMER_WRITE_POST_TCLR, SOC_DMTIMER_7_REGS);
            HWREG(SOC_DMTIMER_7_REGS + DMTIMER_TCLR) |= (DMTIMER_TCLR_PT_TOGGLE << DMTIMER_TCLR_PT_SHIFT);
            // -----output----
            DMTimerGPOConfigure(SOC_DMTIMER_7_REGS, DMTIMER_GPO_CFG_0); // 0 = output enabled, 1 = output disabled
            // -----timer enable-----
            DMTimerIntEnable(SOC_DMTIMER_7_REGS, DMTIMER_INT_OVF_EN_FLAG);
            DMTimerEnable(SOC_DMTIMER_7_REGS);