在采集显示NTSC图像时遇到一个奇怪的问题，就是在采集端DSP设置成按场采集时，没采完一场产生一个中断信号，产生的中断信号频率是30Hz而不是60Hz（????）,按帧采集的频率是30Hz(正确);在输出端DSP设置成按帧输出时，产生的中断信号频率是60Hz(？？？？应该是30Hz)，后来测试按奇场（或偶场）输出完才产生中端，频率都是30Hz，不知道是什么原因，请帮忙分析下，代码如下
输入设置代码：
#include <std.h>
#include <csl.h>
//#include "video_outcfg.h"
/*以下的程序是用DMA方式采集图的的设置、中断、以及数据传输的函数*/
/**********************************************************/
/* Capture parameter definitions based on 525/60 format */
/**********************************************************/
/*NTSC*/
#define VCA_HBLNK_SIZE 138 /* (858-720),horizontal blanking */
#define VCA_IMG_VSIZE1 244 /* (263-20+1), fld1 vertical image size */
#define VCA_IMG_VSIZE2 243 /* (525-283+1), fld2 vertical image size */
#define VCA_VBLNK1_SIZE 19 /* (20.1),v.blanking for field1 */
#define VCA_VBLNK2_SIZE 19 /* (283.264),v.blanking for field2 */
/*PAL*/
//#define VCA_HBLNK_SIZE 144 /* (864-720),horizontal blanking */
/*确定第一场图像的重直像素为288*/
//#define VCA_IMG_VSIZE1 288 /* (311-24+1), fld1 vertical image size */
/*确定第一场图像的重直像素为288*/
//#define VCA_IMG_VSIZE2 288 /* (625-338+1), fld2 vertical image size */
/*确定第一场图像的水平像素为720*/
#define VCA_IMG_HSIZE1 720 /* field1 horizontal image size */
/*确定第二场图像的水平像素为720*/
#define VCA_IMG_HSIZE2 720 /* field2 horizontal image size */
/* 确定一场像素的大小为720×288 */
#define VCA_IMAGE_SIZE1 (VCA_IMG_HSIZE1 * VCA_IMG_VSIZE1)
/* 确定二场像素的大小为720×288 */
#define VCA_IMAGE_SIZE2 (VCA_IMG_HSIZE2 * VCA_IMG_VSIZE2)
/* Define threshold values in double.words. Both fields should have same threshold value*/
/* 确定FIFO的事件的门槛，为一行的长度，因为DM642为64位DMA，所以长度/8 */
#define VCA_VDTHRLD1 (VCA_IMG_HSIZE1/8) /* line length in */
#define VCA_VDTHRLD2 VCA_VDTHRLD1 /* double.words */
/* ....................................................... */
/* Define channel A capture window co-ordinates for Field1 */
/* ....................................................... */
/*设置图像的采集框*/
/* HRST = 0, start of horizontal blanking，HCOUNT在EAV后复位
即一行是从EAV之后开始 ，那行消隐在前，图像在后*/
#define VCA_XSTART1 (VCA_HBLNK_SIZE-2)/*EAV*/
#define VCA_XSTOP1 (VCA_XSTART1 + VCA_IMG_HSIZE1-1)
/* VRST = 1, end of vertical blanking */
#define VCA_YSTART1 1
#define VCA_YSTOP1 (VCA_YSTART1 + VCA_IMG_VSIZE1-1)
/* ....................................................... */
/* Define channel A capture window co-ordinates for Field2 */
/* ....................................................... */
/* HRST = 0, start of horizontal blanking */
#define VCA_XSTART2 (VCA_HBLNK_SIZE-2/*EAV*/)
#define VCA_XSTOP2 (VCA_XSTART2 + VCA_IMG_HSIZE2-1)
/* VRST = 1, end of vertical blanking */
#define VCA_YSTART2 1
#define VCA_YSTOP2 (VCA_YSTART2 + VCA_IMG_VSIZE2-1)
/* Define threshold values in double-words. Both fields should same threshold value */
/* 确定FIFO触发的长度*/
#define VCA_THRLD_FIELD1 (VCA_IMG_HSIZE1/8) /* line length in */
#define VCA_THRLD_FIELD2 VCA_THRLD_FIELD1 /* double-words */
/* Define number of events to be generated for field1 and field2
定义奇场（244）与偶场的行数（243）*/
#define VCA_CAPEVT1 (VCA_IMAGE_SIZE1 / (VCA_VDTHRLD1 * 8))
#define VCA_CAPEVT2 (VCA_IMAGE_SIZE2 / (VCA_VDTHRLD2 * 8))
/* in this example 定义采1帧 */
#define CAPCHA_FRAME_COUNT 1
/* ............................................ */
/* EDMA parameters for capture Y event that are */
/* specific to this example. */
/* ............................................ */
/* because VCA_THRLD_FIELDn is in double-words and element size is 32-bit */
#define VCA_Y_EDMA_ELECNT (VCA_THRLD_FIELD1 * 2)
#define VCA_Y_EDMA_FRMCNT ((VCA_CAPEVT1 + VCA_CAPEVT2) * CAPCHA_FRAME_COUNT)
#define GPIO *((unsigned char *)(0x90080012))
/******************************************************************/
/* Description : 8.bit BT.656 non.continuous frame capture */
/* */
/* Some important field descriptions: */
/* */
/* CMODE = 000, 8.bit BT.656 mode */
/* CON = 0 */
/* FRAME = 1, capture frame */
/* CF2 = 0 */
/* CF1 = 0, (8-bit non.continuous frame capture) */
/* SCALE = 0, no scaling */
/* RESMPL= 0, no resampling */
/* 10BPK = X, not used in 8-bit capture */
/* EXC = 0, use EAV/SAV codes */
/* VRST = 1, end of vertical blanking */
/* HRST = 0, start of horizontal blanking */
/* FLDD = 0, 1st line EAV or FID input */
/* FINV = 0, no field invert */
/* RDFE = X, used in Raw mode only(Enable field identification) */
/* SSE = X, used in Raw mode only(Startup synch enable) */
/******************************************************************/
#include <vportcap.h>
/*................................................................ */
/* global variable declarations */
/* ............................................................... */
#pragma DATA_SECTION(capChaAYSpace, ".capChaAYSpace")
/* buffer to store captured Y-data */
Uint8 capChaAYSpace[720*488];
#pragma DATA_SECTION(capChaACbSpace, ".capChaACbSpace")
/* buffer to store captured Cb-data */
Uint8 capChaACbSpace[360*488];
#pragma DATA_SECTION(capChaACrSpace, ".capChaACrSpace")
/* buffer to store captured Cr-data */
Uint8 capChaACrSpace[360*488];
/* handle of vp that to be configured */
VP_Handle vpCaptureHandle;
/*设置Y、Cb、Cr的EDMA通路的句柄*/
EDMA_Handle hEdmaVPCapChaAY;
EDMA_Handle hEdmaVPCapChaACb;
EDMA_Handle hEdmaVPCapChaACr;
/* EDMA tcc for Y channel */
Int32 edmaCapChaAYTccNum = 0;
/* EDMA tcc for Cb channel */
Int32 edmaCapChaACbTccNum = 0;
/* EDMA tcc for Cb channel */
Int32 edmaCapChaACrTccNum = 0;
/* no of frames captured */
volatile Uint32 capChaAFrameCount = 0;
/* Error flags */
volatile Uint32 capChaAOverrun = 0;
volatile Uint32 capChaASyncError = 0;
volatile Uint32 capChaAShortFieldDetect = 0;
volatile Uint32 capChaALongFieldDetect = 0;
volatile Uint32 capNewFrame = 0;
extern volatile Uint8 Ping_Pong_cap;
extern volatile Uint16 mCounter;
extern volatile Uint8 CapISR_Err;
Int32 EDMA_tcc[10];
Uint32 Tcc_Cnt = 0;
EDMA_Handle EDMA_Table[10];
Uint32 Table_Cnt = 0;
//extern far SWI_obj SWI0;
/*******************************************************************/
/* Function : bt656_8bit_ncfc */
/* Input(s) : portNumber, video port number i.e. 0, 1 or 2. */
/* Description : Configures given video port for 8.bit BT.656 non. */
/* continuos frame capture on channel A. */
/*******************************************************************/
VP_Handle bt656_8bit_ncfc( int portNumber)
{
/* Open video port for capture ,打开一个视频端口*/
vpCaptureHandle = VP_open(portNumber, VP_OPEN_RESET);
if(vpCaptureHandle == INV)
{
return (VP_Handle)0xffff;
}
/* Enable video port functionality in VP Peripheral Control Reg(PCR)，使能视频端口*/
VP_FSETH(vpCaptureHandle, PCR, PEREN, VP_PCR_PEREN_ENABLE);
/* ..................... */
/* Enable all interrupts */
/* ..................... */
/*便能VCA的中断源*/
/* Enable capture overrun interrupt(COVRA) for VP channel A */
VP_FSETH(vpCaptureHandle, VPIE, COVRA, VP_VPIE_COVRA_ENABLE);
/* Enable capture complete interrupt(CCMPA) for VP channel A */
VP_FSETH(vpCaptureHandle, VPIE, CCMPA, VP_VPIE_CCMPA_ENABLE);
/* Enable channel synchronization error interrupt(SERRA) for */
/* VP channel A */
VP_FSETH(vpCaptureHandle, VPIE, SERRA, VP_VPIE_SERRA_ENABLE);
/* Enable short field detect interrupt(SFDA) for VP channel A */
VP_FSETH(vpCaptureHandle, VPIE, SFDA, VP_VPIE_SFDA_ENABLE);
/* Enable video port global interrupt enable */
VP_FSETH(vpCaptureHandle, VPIE, VIE, VP_VPIE_VIE_ENABLE);
/* ...................... */
/* Setup all other fields */
/* ...................... */
/* Enable short field detect，使苋背√讲?/
VP_FSETH(vpCaptureHandle, VCACTL, SFDE, VP_VCACTL_SFDE_ENABLE);
/* Set last pixel to be captured in Field1 (VCA_STOP1 reg) */
/*设置第一场的最后一个像素的Y轴与X轴的坐标*/
VP_RSETH(vpCaptureHandle, VCASTOP1,VP_VCASTOP1_RMK(VCA_YSTOP1, VCA_XSTOP1));
/* Set last pixel to be captured in Field2 (VCA_STOP2 reg) */
/*设置第二场的最后一个像素的Y轴与X轴的坐标*/
VP_RSETH(vpCaptureHandle, VCASTOP2,VP_VCASTOP2_RMK(VCA_YSTOP2, VCA_XSTOP2));
/* Set first pixel to be captured in Field1 (VCA_STRT1 reg) */
/*设置第一场的第一个像素的Y轴与X轴的坐标*/
VP_RSETH(vpCaptureHandle, VCASTRT1, VP_VCASTRT1_RMK(VCA_YSTART1,VP_VCASTRT1_SSE_ENABLE, VCA_XSTART1));
/* Set first pixel to be captured in Field2 (VCA_STRT2 reg) */
/*设置第二场的第一个像素的Y轴与X轴的坐标*/
VP_RSETH(vpCaptureHandle, VCASTRT2,VP_VCASTRT2_RMK(VCA_YSTART2, VCA_XSTART2));
/* Set threshold values ，设置EDMA启动的门限*/
VP_RSETH(vpCaptureHandle, VCATHRLD,VP_VCATHRLD_RMK(VCA_THRLD_FIELD2, VCA_THRLD_FIELD1));
/* Set capture event.register values，设置一场的需要的EDMA的次数 */
VP_RSETH(vpCaptureHandle, VCAEVTCT,VP_VCAEVTCT_RMK(VCA_CAPEVT2,VCA_CAPEVT1));
/* Vertical interrupts (VCA_INT) are not enabled in this example. */
/* Set CMODE to 8.bit BT.656，采用BT656格式的数据流 */
VP_FSETH(vpCaptureHandle, VCACTL, CMODE, VP_VCACTL_CMODE_BT656B);
/* Set non.continuous frame capture，设置为电视显示格式的采集，即不连续的采集，
CON/FRAME/CF2/CF1的值为0100 */
VP_FSETH(vpCaptureHandle, VCACTL, CON, VP_VCACTL_CON_DISABLE);
VP_FSETH(vpCaptureHandle, VCACTL, FRAME, VP_VCACTL_FRAME_FRMCAP);// VP_VCACTL_FRAME_FRMCAP
VP_FSETH(vpCaptureHandle, VCACTL, CF2, VP_VCACTL_CF2_NONE);
VP_FSETH(vpCaptureHandle, VCACTL, CF1, VP_VCACTL_CF1_NONE);
/* Let FLDD and FINV to be their defaults */
/* Set VRST to end of vertical blanking,VCOUNT复位在场消隐之后 */
VP_FSETH(vpCaptureHandle, VCACTL, VRST, VP_VCACTL_VRST_V0EAV);
/* Set HRST to start of horizontal blanking，行计数复位在EAV之后 */
VP_FSETH(vpCaptureHandle, VCACTL, HRST, VP_VCACTL_HRST_OF(0));
/* 10.bit pack mode(10BPK bit) in this 8.bit example */
/* No (1/2) scaling and no chroma re.sampling in this example */
/*初始化EDMA通路*/
IRQ_enable(IRQ_EVT_VINT1);
/* Enable video port interrupts */
IRQ_enable(vpCaptureHandle->eventId);
/* Setup Y, Cb and Cr EDMA channels */
setupVPCapChaAEDMA(portNumber);
/* Clear VPHLT in VP_CTL to make video port function，清除VPHLT位?
使能其它位 */
VP_FSETH(vpCaptureHandle, VPCTL, VPHLT, VP_VPCTL_VPHLT_CLEAR);
/* .............. */
/* enable capture */
/* .............. */
/* set VCEN bit to enable capture，使能VCA口 */
VP_FSETH(vpCaptureHandle, VCACTL, VCEN, VP_VCACTL_VCEN_ENABLE);
/* clear BLKCAP in VCA_CTL to enable capture DMA events */
VP_FSETH(vpCaptureHandle, VCACTL, BLKCAP,VP_VCACTL_BLKCAP_CLEAR);
return (vpCaptureHandle);
}
/*******************************************************************/
/* Function : bt656_capture_start */
/* Input(s) : VP_handle */
/* Description : Configures given video port for 8.bit BT.656 non. */
/* continuos frame capture on channel A. */
/*******************************************************************/
void bt656_capture_start(VP_Handle videoHandle)
{
}
/*................................................................ */
/* Function : VPCapChaAIsr */
/* Description : This capture ISR clears FRMC to continue capture */
/* in this non.continuous mode and also clears other */
/* status bits. */
/*................................................................ */
interrupt void VPCapChaAIsr(void)
{
Uint32 vpis = 0;
/* Get video port status register value */
//IRQ_disable(IRQ_EVT_GPINT5);
vpis = VP_RGETH(vpCaptureHandle, VPIS);
if(vpis & _VP_VPIS_CCMPA_MASK) /* capture complete */
{
/* Clear frame complete bit in VCX_CTL to continue capture in non-continuous mode*/
VP_FSETH(vpCaptureHandle, VCASTAT, FRMC,VP_VCASTAT_FRMC_CLEAR);
/* Clear CCMPA to enable next frame complete interrupts*/
VP_FSETH(vpCaptureHandle, VPIS, CCMPA,VP_VPIS_CCMPA_CLEAR);
capChaAFrameCount++; /* increment captured frame count */
capNewFrame = 1;
Ping_Pong_cap++;
//SWI_post(&SWI1);
//SWI_post(&SWI0);
}
if(vpis & _VP_VPIS_COVRA_MASK) /* overrun error */
{
capChaAOverrun++;
VP_FSETH(vpCaptureHandle, VPIS, COVRA,VP_VPIS_COVRA_CLEAR);
}
if(vpis & _VP_VPIS_SERRA_MASK) /* synchronization error */
{
capChaASyncError++;
VP_FSETH(vpCaptureHandle, VPIS, SERRA,VP_VPIS_SERRA_CLEAR);
}
if(vpis & _VP_VPIS_SFDA_MASK) /* short field detect */
{
capChaAShortFieldDetect++;
VP_FSETH(vpCaptureHandle, VPIS, SFDA, VP_VPIS_SFDA_CLEAR);
}
if(vpis & _VP_VPIS_LFDA_MASK) /* long field detect */
{
capChaALongFieldDetect++;
VP_FSETH(vpCaptureHandle, VPIS, LFDA, VP_VPIS_LFDA_CLEAR);
}
//IRQ_enable(IRQ_EVT_GPINT5);
}
输出设置代码：
#include <std.h>
#include <csl.h>
//#include "video_outcfg.h"
#include <csl_gpio.h>
extern Uint32 SDRAM;
#define GPIO *((unsigned char *)(0x90080012))
/* ................. */
/* Define frame size */
/* ................. */
/* no of pixels per frame line including horizontal blanking*/
/*定义每行的像素数，包括消隐行*/
#define VD_FRM_WIDTH 858
/*定义每帧的行数，包括消隐行*/
#define VD_FRM_HEIGHT 525 /* total noof lines per frame */
/*定义每帧的大小*/
#define VD_FRM_SIZE (VD_FRM_WIDTH * VD_FRM_HEIGHT)
/* ................... */
/* Horizontal blanking */
/* ................... */
/*行消隐出现的像素位置*/
#define VD_HBLNK_START 720 /* starting location of EAV */
/*行消急结束的像素位置*/
#define VD_HBLNK_STOP 856 /* starting location of SAV */
/*消隐的像素数*/
#define VD_HBLNK_SIZE (VD_HBLNK_STOP - VD_HBLNK_START +2/*EAV*/) /* (138) EAV, SAV inclusive */
/* ............................ */
/* Vertical blanking for field1 */
/* ............................ */
/*奇场的场消隐设置*/
#define VD_VBLNK_XSTART1 720 /* pixel on which VBLNK active */
/* edge occurs for field1 */
#define VD_VBLNK_YSTART1 1 /* line on which VBLNK active */
/* edge occurs for field1 */
#define VD_VBLNK_XSTOP1 720 /* pixel on which VBLNK inactive */
/* edge occurs for field1 */
#define VD_VBLNK_YSTOP1 20 /* line on which VBLNK inactive */
/* edge occurs for field1 */
/* ............................ */
/* Vertical blanking for field2 */
/* ............................ */
/*偶场的场消隐设置*/
#define VD_VBLNK_XSTART2 360 /* pixel on which VBLNK active */
/* edge occurs for field2 */
#define VD_VBLNK_YSTART2 263 /* line on which VBLNK active */
/* edge occurs for field2 */
#define VD_VBLNK_XSTOP2 360 /* pixel on which VBLNK inactive */
/* edge occurs for field2 */
#define VD_VBLNK_YSTOP2 283 /* line on which VBLNK inactive */
/* edge occurs for field2 */
/* ................................................. */
/* Define vertical blanking bit(VD_VBITn) reg values */
/* ................................................. */
/*第一场重直消隐设置与清除的所在的行数*/
/* first line with an EAV with V=1 indicating the start of Field1 vertical blanking */
#define VD_VBIT_SET1 1
/* first line with an EAV with V=0 indicating the start of Field1 active display*/
#define VD_VBIT_CLR1 20
#define VD_VBLNK1_SIZE (VD_VBIT_CLR1 - VD_VBIT_SET1) /* 19 lines */
/*第二场重直消隐设置与清除的所在的行数*/
/* first line with an EAV with V=1 indicating the start of Field2 vertical blanking*/
#define VD_VBIT_SET2 264
/* first line with an EAV with V=0 indicating the start of Field2 active display*/
#define VD_VBIT_CLR2 283
#define VD_VBLNK2_SIZE (VD_VBIT_CLR2 - VD_VBIT_SET2) /* 19 lines */
/* ............ */
/* Field timing */
/* ............ */
/* pixel on the first line of Field1 on which FLD ouput is de-asserted*/
#define VD_FIELD1_XSTART 720
/* line on which FLD is de-asserted */
#define VD_FIELD1_YSTART 1
/* pixel on the first line of Field1 on which FLD ouput is asserted */
#define VD_FIELD2_XSTART 360
/* line on which FLD is asserted */
#define VD_FIELD2_YSTART 263
/* .................................... */
/* Define field bit(VD_FBIT) reg values */
/* .................................... */
#define VD_FBIT_CLR 4 /* first line with an EAV with F=0 indicating Field 1 display*/
#define VD_FBIT_SET 266 /* first line with an EAV with F=1 indicating Field 2 display*/
/* ................................ */
/* Define horzontal synchronization */
/* ................................ */
#define VD_HSYNC_START 736
#define VD_HSYNC_STOP 800
/* .......................................... */
/* Define vertical synchronization for field1 */
/* .......................................... */
#define VD_VSYNC_XSTART1 720
#define VD_VSYNC_YSTART1 4
#define VD_VSYNC_XSTOP1 720
#define VD_VSYNC_YSTOP1 7
/* .......................................... */
/* Define vertical synchronization for field2 */
/* .......................................... */
#define VD_VSYNC_XSTART2 360
#define VD_VSYNC_YSTART2 266
#define VD_VSYNC_XSTOP2 360
#define VD_VSYNC_YSTOP2 269
/* ........................................ */
/* Define image offsets for both the fields */
/* which are zero in this example */
/* ........................................ */
#define VD_IMG_HOFF1 0
#define VD_IMG_VOFF1 0
#define VD_IMG_HOFF2 0
#define VD_IMG_VOFF2 0
/* ................................................. */
/* Define image active vertical and horizontal sizes */
/* ................................................. */
#define VD_IMG_HSIZE1 720 /* field1 horizontal image size */
#define VD_IMG_VSIZE1 244 /* field1 vertical image size */
#define VD_IMG_HSIZE2 720 /* field2 horizontal image size */
#define VD_IMG_VSIZE2 243 /* field2 vertical image size */
/* Manipulate field1 and field2 image sizes */
#define VD_IMAGE_SIZE1 (VD_IMG_HSIZE1 * VD_IMG_VSIZE1)
#define VD_IMAGE_SIZE2 (VD_IMG_HSIZE2 * VD_IMG_VSIZE2)
/* Define threshold values in double-words. Both fields should */
/* have same threshold value */
#define VD_VDTHRLD1 (VD_IMG_HSIZE1/8) /* line length in */
#define VD_VDTHRLD2 VD_VDTHRLD1 /* double-words */
/* Define number of events to be generated for field1 and field2 */
#define VD_DISPEVT1 (VD_IMAGE_SIZE1 / (VD_VDTHRLD1 * 8))
#define VD_DISPEVT2 (VD_IMAGE_SIZE2 / (VD_VDTHRLD2 * 8))
#define DISPLAY_FRAME_COUNT 1 /* in this example */
/* ............................................ */
/* EDMA parameters for display Y event that are */
/* specific to this example. */
/* ............................................ */
/* VD_VDTHRLDn is in double-words and 32-bit element size */
#define VD_Y_EDMA_ELECNT (VD_VDTHRLD1 * 2)
#define VD_Y_EDMA_FRMCNT ((VD_DISPEVT1 + VD_DISPEVT2) * DISPLAY_FRAME_COUNT)
/******************************************************************/
/* Description : 8.bit BT.656 non.continuous frame display */
/* */
/* Some important field descriptions: */
/* */
/* DMODE = 000, 8.bit BT.656 mode */
/* CON = 0 */
/* FRAME = 1, display frame */
/* DF2 = 0 */
/* DF1 = 0, (8.bit non.continuous frame display) */
/* SCALE = 0, no scaling */
/* RESMPL = 0, no resampling */
/* DPK = X, not used in 8.bit display */
/* RSYNC = X, used in Raw mode(Enable second synchronized raw */
/* data channel) */
/* RGBX = X, used in Raw mode(RGB extract enable. Perform */
/* 3/4 FIFO unpacking) */
/* VCTL1S = 00, output HSYNC */
/* VCTL2S = 00, output VSYNC */
/* VCTL3S = 0, output CBLNK */
/* HXS = 0, VCTL1 is an output */
/* VXS = 0, VCTL2 is an output */
/* FXS = 0, VCTL3 is an output */
/* PVPSYN = 0, no previous port synchronization */
/******************************************************************/
#include <vportdis.h>
#include "vportcap.h"
/*................................................................ */
/* global variable declarations */
/* ............................................................... */
// Uint32 disChaAYSpace = 0x80000000;
// Uint32 disChaACbSpace = 0x800675c0;
// Uint32 disChaACrSpace = 0x8009b0a0;
#pragma DATA_SECTION(disChaAYSpace, ".disChaAYSpace")
/* buffer to store captured Y-data */
Uint8 disChaAYSpace[720*488];
#pragma DATA_SECTION(disChaACbSpace, ".disChaACbSpace")
/* buffer to store captured Cb-data */
Uint8 disChaACbSpace[360*488];
#pragma DATA_SECTION(disChaACrSpace, ".disChaACrSpace")
/* buffer to store captured Cr-data */
Uint8 disChaACrSpace[360*488];
/* handle of vp that to be configured */
VP_Handle vpDisplayHandle;
EDMA_Handle hEdmaVPDispY;
EDMA_Handle hEdmaVPDispCb;
EDMA_Handle hEdmaVPDispCr;
Int32 edmaDispYTccNum = 0; /* EDMA tcc for Y channel */
Int32 edmaDispCbTccNum = 0; /* EDMA tcc for Cb channel */
Int32 edmaDispCrTccNum = 0; /* EDMA tcc for Cb channel */
volatile Uint32 displayFrameCount = 0; /* no of frames that are */
/* displayed */
volatile Uint32 dispUnderrun = 0; /* underrun error flag */
volatile Uint32 disNewFrame =0;
extern volatile Uint8 Ping_Pong_dis;
extern GPIO_Handle hGpio;//IO句柄
extern Uint8 Led0;
/*................................................................ */
/* Function : bt656_8bit_ncfd */
/* Input(s) : portNumber, video port number i.e. 0, 1 or 2. */
/* Description : Configures given video port for 8.bit BT.656 non. */
/* continuous frame display. */
/*................................................................ */
VP_Handle bt656_8bit_ncfd(int portNumber)
{
/* Open video port for display ，打开一个视频口*/
vpDisplayHandle = VP_open(portNumber, VP_OPEN_RESET);
if(vpDisplayHandle == INV)
{
return (VP_Handle)0xFFFF;
}
/*使能视频口*/
/* Enable video port functionality in VP Peripheral Control Reg(PCR)*/
VP_FSETH(vpDisplayHandle , PCR, PEREN, VP_PCR_PEREN_ENABLE);
/* Set this port to display mode，将此口设为显示模式 */
VP_FSETH(vpDisplayHandle , VPCTL, DISP, VP_VPCTL_DISP_DISPLAY);
/* ..................... */
/* Enable all interrupts */
/* ..................... */
/*使能相应的中断源*/
/* enable display complete interrupt */
VP_FSETH(vpDisplayHandle , VPIE, DCMP, VP_VPIE_DCMP_ENABLE);
/* enable display underrun interrupt */
VP_FSETH(vpDisplayHandle , VPIE, DUND, VP_VPIE_DUND_ENABLE);
/* enable video port global interrupt enable */
VP_FSETH(vpDisplayHandle , VPIE, VIE, VP_VPIE_VIE_ENABLE);
/* .................... */
/* Set all other fields */
/* .................... */
/* set frame size ，设置显示帧的大小*/
VP_RSETH(vpDisplayHandle , VDFRMSZ,VP_VDFRMSZ_RMK(VD_FRM_HEIGHT, VD_FRM_WIDTH));
/*设置信号VBLNK的时序*/
/* set horizontal blanking，设置水平消隐的起始位置与停止位置720～856 */
VP_RSETH(vpDisplayHandle , VDHBLNK,VP_VDHBLNK_RMK(VD_HBLNK_STOP,
VP_VDHBLNK_HBDLA_NONE,
VD_HBLNK_START));
/* set vertical blanking start for field1，设置第一场的垂直消隐的位置 */
VP_RSETH(vpDisplayHandle , VDVBLKS1,VP_VDVBLKS1_RMK(VD_VBLNK_YSTART1,
VD_VBLNK_XSTART1));
/* set vertical blanking end for field1 */
VP_RSETH(vpDisplayHandle , VDVBLKE1,VP_VDVBLKE1_RMK(VD_VBLNK_YSTOP1,
VD_VBLNK_XSTOP1));
/* set vertical blanking start for field2 ，设置第二场的垂直消隐的位置*/
VP_RSETH(vpDisplayHandle , VDVBLKS2,VP_VDVBLKS2_RMK(VD_VBLNK_YSTART2,
VD_VBLNK_XSTART2));
/* set vertical blanking end for field2 */
VP_RSETH(vpDisplayHandle , VDVBLKE2,VP_VDVBLKE2_RMK(VD_VBLNK_YSTOP2,
VD_VBLNK_XSTOP2));
/*设置EAV与SAV中的V位的值*/
/* set vertical blanking bit register for field 1(VD_VBIT1) */
/*设置第一场的消隐的行数*/
VP_RSETH(vpDisplayHandle , VDVBIT1,VP_VDVBIT1_RMK(VD_VBIT_CLR1,
VD_VBIT_SET1));
/* set vertical blanking bit register for field 2(VD_VBIT2) */
/*设置第二场的消隐的行数*/
VP_RSETH(vpDisplayHandle , VDVBIT2,VP_VDVBIT2_RMK(VD_VBIT_CLR2,
VD_VBIT_SET2));
/* No image offsets in this example */
/* set image size for field1,每一场设置图像的大小 */
VP_RSETH(vpDisplayHandle , VDIMGSZ1,VP_VDIMGSZ1_RMK(VD_IMG_VSIZE1,
VD_IMG_HSIZE1));
/* set image size for field2，设置第二场图像的大小 */
VP_RSETH(vpDisplayHandle , VDIMGSZ2,VP_VDIMGSZ1_RMK(VD_IMG_VSIZE2,
VD_IMG_HSIZE2));
/*设置FLD信号的逻辑*/
/* set field1 timing ，设置第一场的起始点*/
VP_RSETH(vpDisplayHandle , VDFLDT1,VP_VDFLDT1_RMK(VD_FIELD1_YSTART, VD_FIELD1_XSTART));
/* set field2 timing ，设置第二场的起始点*/
VP_RSETH(vpDisplayHandle , VDFLDT2,VP_VDFLDT2_RMK(VD_FIELD2_YSTART, VD_FIELD2_XSTART));
/*设置EAV与SAV中的F位的值*/
/* set display field bit register(VD_FBIT) */
VP_RSETH(vpDisplayHandle , VDFBIT,VP_VDFBIT_RMK(VD_FBIT_SET, VD_FBIT_CLR));
/* set horizontal sync control (VCTL1S) ，设置水平同步信号输出的控制*/
VP_RSETH(vpDisplayHandle , VDHSYNC,VP_VDHSYNC_RMK(VD_HSYNC_STOP, VD_HSYNC_START));
/*设置重直同步信号输出的控制*/
/* set vertical sync start for field1 (VCTL1S) */
VP_RSETH(vpDisplayHandle , VDVSYNS1,VP_VDVSYNS1_RMK(VD_VSYNC_YSTART1,VD_VSYNC_XSTART1));
/* set vertical sync end for field1 (VCTL1S) */
VP_RSETH(vpDisplayHandle , VDVSYNE1,VP_VDVSYNE1_RMK(VD_VSYNC_YSTOP1, VD_VSYNC_XSTOP1));
/* set vertical sync start for field2 (VCTL2S) */
VP_RSETH(vpDisplayHandle , VDVSYNS2,VP_VDVSYNS2_RMK(VD_VSYNC_YSTART2,VD_VSYNC_XSTART2));
/* set vertical sync end for field2 (VCTL2S) */
VP_RSETH(vpDisplayHandle , VDVSYNE2,VP_VDVSYNE2_RMK(VD_VSYNC_YSTOP2, VD_VSYNC_XSTOP2));
/* Let clipping values to be their defaults (VD_CLIP) No need to set DEF_VAL and VD_RELOAD in this example*/
/*设置中断事件*/
/* set event register */
VP_RSETH(vpDisplayHandle , VDDISPEVT,VP_VDDISPEVT_RMK(VD_DISPEVT2, VD_DISPEVT1));
/* Vertical interrupts are not used in this example (VD_VINT) */
/* set threshold value for DMA events */
VP_RSETH(vpDisplayHandle, VDTHRLD,VP_VDTHRLD_RMK(VD_VDTHRLD2,
VP_VDTHRLD_INCPIX_DEFAULT,
VD_VDTHRLD1));
/* ............................... */
/* Set display control reg(VD_CTL) */
/* ............................... */
/* set display mode(DMODE) to 8-bit BT.656 */
VP_FSETH(vpDisplayHandle , VDCTL, DMODE, VP_VDCTL_DMODE_BT656B);
/* set non-continuous frame display */
VP_FSETH(vpDisplayHandle , VDCTL, CON, VP_VDCTL_CON_DISABLE);
VP_FSETH(vpDisplayHandle , VDCTL, FRAME, VP_VDCTL_FRAME_FRMDIS);//FRMDIS
VP_FSETH(vpDisplayHandle , VDCTL, DF2, VP_VDCTL_DF2_NONE);
VP_FSETH(vpDisplayHandle , VDCTL, DF1, VP_VDCTL_DF1_NONE);
/* let control outputs(VCTL1S, VCTL2S, VCTL3S, HXS, VXS, FXS) */
/* be their defaults i.e. VCTLxS are output control signals */
/* no scaling and no resampling in this example */
/* no need to bother about 10.bit unpacking mode(DPK bit) */
/* in this 8.bit example */
/* Set up Y, Cb and Cr EDMA channels */
setupVPDispEDMA(portNumber);
IRQ_enable(vpDisplayHandle ->eventId);
/* clear VPHLT in VP_CTL to make video port function */
VP_FSETH(vpDisplayHandle , VPCTL, VPHLT, VP_VPCTL_VPHLT_CLEAR);
return vpDisplayHandle;
}
