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C6657LS EVM运行Timer样例时间问题

在C6657LS EVM上运行Timer样例,样例中Timer的周期设置为1ms,系统工作频率为1GHz,KeyStone_main_PLL_init(100, 10, 1);

在Timer中断服务程序中增加了DSP滴答时戳

void interrupt Timer_ISR(void)
{
 uiTick++;
 tscl= TSCL;
 tsch= TSCH;
 printf("\n %d times, Timer_ISR at DSP-CYCLE %lld \n",uiTick, _itoll(tsch, tscl));

}

程序加载到C66xx_0,运行结果如下:

[[C66xx_0] Initialize DSP main clock = 100.00MHz/1x10 = 1000MHz
[C66xx_0] Enable Exception handling...
[C66xx_0]
[C66xx_0] a pulse will be generated on TIMO0...
[C66xx_0]
[C66xx_0]  1 times, Timer_ISR at DSP-CYCLE 2000005837
[C66xx_0] a pulse was generated on TIMO0
[C66xx_0]
[C66xx_0] clocks will be generated on TIMO0...
[C66xx_0]
[C66xx_0]  1 times, Timer_ISR at DSP-CYCLE 2000519445
[C66xx_0]
[C66xx_0]  2 times, Timer_ISR at DSP-CYCLE 2000529193
[C66xx_0] External exception happened. MEXPFLAG[3]=0x1.
[C66xx_0]   Event 96: DSP Interrupt 14 (INTC input Event 64) dropped
[C66xx_0] NRP=0xc0085a6, NTSR=0x1000d, IRP=0xc0085a6, ITSR=0xd, TSCH= 0x0, TSCL= 0x773dcd59
[C66xx_0]  B3=0xc008584, A4=0x30, B4= 0x3e8, B14= 0x802128, B15= 0x8011d0
[C66xx_0]
[C66xx_0]  3 times, Timer_ISR at DSP-CYCLE 2000591788
[C66xx_0]

。。。。

 [C66xx_0]  1058 times, Timer_ISR at DSP-CYCLE 2011041780
[C66xx_0]
[C66xx_0]  1059 times, Timer_ISR at DSP-CYCLE 2011051789
[C66xx_0]
[C66xx_0]  1060 times, Timer_ISR at DSP-CYCLE 2011061799
[C66xx_0]
[C66xx_0]  1061 times, Timer_ISR at DSP-CYCLE 2011071808
[C66xx_0]
[C66xx_0]  1062 times, Timer_ISR at DSP-CYCLE 2011081817
[C66xx_0]
[C66xx_0]  1063 times, Timer_ISR at DSP-CYCLE 2011091826

在Timer-ISR中前后DSP_Cycle差约为10400,若是1ms对应的DSP-cycle是10400,好像差异很大,DSP-CYCLE时间该怎么计算?

另外,依据Timer例程,

 while(uiTick<NUM_CLOCKS_GENERATED*2)
  asm(" nop 5");
 Reset_Timer(DNUM);  //stop the timer

该中断应该运行NUM_CLOCKS_GENERATED(500)*2 = 1000次后终止,改到运行start watch-dog timer...,但是Timer_ISR一直运行下去,是哪出错了吗?

运行结果中的 Event 96: DSP Interrupt 14 (INTC input Event 64) dropped,说明什么问题呢?

 

将.out加载到C66xx_1核运行,输出如下:

[C66xx_1]  993 times, Timer_ISR at DSP-CYCLE 2496499416
[C66xx_1]
[C66xx_1]  994 times, Timer_ISR at DSP-CYCLE 2496999392
[C66xx_1]
[C66xx_1]  995 times, Timer_ISR at DSP-CYCLE 2497499374
[C66xx_1]
[C66xx_1]  996 times, Timer_ISR at DSP-CYCLE 2497999348
[C66xx_1]
[C66xx_1]  997 times, Timer_ISR at DSP-CYCLE 2498499336
[C66xx_1]
[C66xx_1]  998 times, Timer_ISR at DSP-CYCLE 2498999312
[C66xx_1]
[C66xx_1]  999 times, Timer_ISR at DSP-CYCLE 2499499299
[C66xx_1]
[C66xx_1]  1000 times, Timer_ISR at DSP-CYCLE 2499999283
[C66xx_1] clocks were generated on TIMO0
[C66xx_1]
[C66xx_1] start watch-dog timer...
[C66xx_1] service watch-dog 1 times, at time counter = 6
[C66xx_1] service watch-dog 2 times, at time counter = 1678
[C66xx_1] service watch-dog 3 times, at time counter = 1723
[C66xx_1] service watch-dog 4 times, at time counter = 1723
[C66xx_1] service watch-dog 5 times, at time counter = 1724
[C66xx_1] service watch-dog 6 times, at time counter = 1723

 

在Timer-ISR中前后DSP_Cycle差约为500000,这能表示Timer的周期为1ms吗?以上测试数据,请大侠帮忙分析问题出在哪,非常感谢!

  • 注意例程中timer使用时钟源为internal clock,所以timer时钟源为1/6*CPU_CLOCK,即如果CPU工作在1GHz,则Timer计时单位为1/6ns,timer产生的中断周期也是可以配的。

    这里你可以根据Timer ISR中记录相邻两次的TSC时间相减,得到timer中断周期,这个时间是根据CPU CLOCK为单位得到的,即工作主频为1GHz,单位为1ns,根据这个时间再与之前配置的timer period比较是否一致。

  • Andy,您好!谢谢您的回复

    在计算Timer中断的周时,样例程序是按照1/6*CPU_CLOCK计算的,设置Timer为周期工作方式,周期为1ms,在C66xx_0中打印出的TSC时间间隔约为1400,按照1GHz的CPU频率,10400为10.4us。在C66xx_1中运行,中打印出的TSC时间间隔约为500000,按照1GHz的CPU频率,500000为0.5ms。不管是C66xx_0的运行结果还是C66xx_1的运行结果和Timer设置的1ms周期不对应,该怎么理解?谢谢!

  • timer工作在clock mode时,两个时钟周期产生一个clock,一半是高电平,一般是低电平,所以配置clock为1ms时,输出的timer信号是0.5ms。另外我测试在timer ISR中记录core0也是0.5ms周期。

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