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TMS320VC5407 CLOCKOUT输出频率问题？

qiusheng zhang
Prodigy 50 points
Other Parts Discussed in Thread: TMS320VC5404, TMS320VC5407

用16.384M的晶振接到X2/CLKIN,X1悬空，CLKMOD设置0x37fe,用示波器测试CLKOUT是16.384M，CLKMOD改为0X47FE，用示波器测试为20.48MHZ;

当CLKMOD设置为0x37fe，CLKOUT不是应该是CLKIN*系数=16.384*（3+1）=65.536MHZ吗？怎么会是16.384MHZ呢，

当CLKMOD设置为0x47fe，CLKOUT不是应该是CLKIN*系数=16.384*（4+1）=81.92MHZ吗？怎么会是20.48MHZ呢，

请知道的尽快恢复我，先谢谢大家了！

  • 0
    Genius 3060 points

    看了一下TMS320VC5407/TMS320VC5404 Fixed-Point Digital Signal Processors的datasheet，中描述

    • PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.

    • DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can

    be completely disabled in order to minimize power dissipation.

    但是你的CLKMD寄存器设置的是e，设置成了DIV模式。

    0  PLLSTATUS PLL status. Indicates the mode that the clock generator is operating.

    PLLSTATUS = 0 Divider (DIV) mode

    PLLSTATUS = 1 PLL mode