我是用openocd调试AM1808，在init文件里面初始化PLL0和PLL1，初始化PLL0时，发现设置PLLCMD的GO位时，仿真器死机了，
提示如下
Warn : Bad value '01C11104' captured during DR or IR scan:
Warn : check_value: 0x00000009
Warn : check_mask: 0x00000009 Error: JTAG error while reading cpsr
我设置PLLM=24，PLLPOSTDIV=1，PLL的频率为600M，输出为300M
我把这个配置数据加载到PLL1，可以正常输出300M
我开始做了第二个实验
我把PLLCMD的GO位不操作，因为我用的缺省的DIV数据，但是执行PLLCTL里面的PLLEN位时，仿真器同样死机，提示一样
附上我的ocd命令
大家帮我看看
PLL1可以设置成功，PLL0不行
帮我找找原因
#************************************************************************* # gdb port #*************************************************************************
telnet_port 8023
gdb_port 1000
#*************************************************************************
# interface
#*************************************************************************
interface ft2232
ft2232_device_desc "USB<=>JTAG&RS232 A"
ft2232_layout jtagkey
ft2232_vid_pid 0x1457 0x5118
adapter_khz 500
#*************************************************************************
# chip name
#*************************************************************************
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omapl138
}
source [find target/icepick.cfg]
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2B900F0F
}
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xF -expected-id $_ETB_TAPID -disable
jtag configure $_CHIPNAME.etb -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 3"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x07926001
}
jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xF -expected-id $_CPU_TAPID -disable
jtag configure $_CHIPNAME.arm -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 2"
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b7d102f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3F -expected-id $_JRC_TAPID -ignore-version
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
# $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
$_TARGETNAME configure -work-area-phys 0xFFFF0000 -work-area-size 0x2000
$_TARGETNAME configure -event "reset-start" { adapter_khz 500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
gdb_breakpoint_override hard
arm7_9 dbgrq enable
reset_config trst_and_srst separate
proc mrw {reg} {
set value ""
mem2array value 32 $reg 1
return $value(0)
}
#*************************************************************************
# phyaddr define
#*************************************************************************
global AM1808
set AM1808 [ dict create ]
dict set AM1808 pllc1 0x01C11000
dict set AM1808 pllc2 0x01E1A000
dict set AM1808 psc0 0x01C10000
dict set AM1808 psc1 0x01E27000
proc pll0_setup {pll_addr mult} {
mdw 0x01C11000
#############################################################
# init pll_ctrl_addr
set pll_ctrl_addr [expr $pll_addr + 0x100]
set pll_ctrl [mrw $pll_ctrl_addr]
#############################################################
# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
# NOTE: this assumes we should clear that bit
set pll_ctrl [ expr $pll_ctrl & ~0x100 ]
mww $pll_ctrl_addr $pll_ctrl
echo "clear CLKMODE BIT8"
mdw $pll_ctrl_addr
#############################################################
# 2 - clear EXTCLKSRC (bit 9) for Use OSCIN for the PLL bypass clock
set pll_ctrl [expr $pll_ctrl & ~0x0200]
mww $pll_ctrl_addr $pll_ctrl
echo "EXTCLKSRC BIT9"
mdw $pll_ctrl_addr
#############################################################
# 3 - clear PLLENSRC BIT5 for This bit must be cleared before the PLLEN bit will have any effect
set pll_ctrl [expr $pll_ctrl & ~0x0020]
mww $pll_ctrl_addr $pll_ctrl
echo "clear PLLENSRC (bit 5)"
mdw $pll_ctrl_addr
#############################################################
# 4 - clear PLLEN BIT0 enter bypass mode
set pll_ctrl [expr $pll_ctrl & ~0x0001]
mww $pll_ctrl_addr $pll_ctrl
echo "clear PLLEN (bit 0) for bypass"
mdw $pll_ctrl_addr
#############################################################
# 5 - wait at least 4 refclk cycles
sleep 1
#############################################################
# 6 - clear PLLRST BIT3 for PLL0 reset is asserted
set pll_ctrl [expr $pll_ctrl & ~0x0008]
mww $pll_ctrl_addr $pll_ctrl
echo "clear PLLRST BIT3 reset"
mdw $pll_ctrl_addr
#############################################################
# 8 - clear PLLPWRDN BIT1 for PLL0 is operating
set pll_ctrl [expr $pll_ctrl & ~0x0002]
mww $pll_ctrl_addr $pll_ctrl
echo "clear PLLPWRDN BIT1 run"
mdw $pll_ctrl_addr
#############################################################
# 10 write prediv, postdiv, and pllm
set div [expr 0x8000 | 0]
mww [expr $pll_addr + 0x0114] $div
echo "set prediv"
mdw [expr $pll_addr + 0x0114]
#############################################################
# 10 write pllm
mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xFF]
echo "set pllm"
mdw [expr $pll_addr + 0x0110]
#############################################################
# 10 write postdiv
set div [expr 0x8000 | 1]
mww [expr $pll_addr + 0x0128] $div
echo "set postdiv"
mdw [expr $pll_addr + 0x0128]
mdw [expr $pll_addr + 0x0118]
mdw [expr $pll_addr + 0x011C]
mdw [expr $pll_addr + 0x0120]
mdw [expr $pll_addr + 0x0160]
mdw [expr $pll_addr + 0x0164]
mdw [expr $pll_addr + 0x0168]
mdw [expr $pll_addr + 0x016C]
#############################################################
# write go CMD
# mww [expr $pll_addr + 0x0138] 0x01
# sleep 800
# echo "set CMD go"
# mdw [expr $pll_addr + 0x0138]
#############################################################
# 11 - wait at least 5 usec for reset to finish
sleep 20
#############################################################
# 12 set PLLRST BIT3
set pll_ctrl [expr $pll_ctrl | 0x0008]
mww $pll_ctrl_addr $pll_ctrl
echo "set PLLRST BIT3 out reset"
mdw $pll_ctrl_addr
#############################################################
# 13 - wait at least 8000 refclk cycles for PLL to lock
sleep 800
#############################################################
# 14 - set PLLEN BIT0 leave bypass mode
set pll_ctrl [expr $pll_ctrl | 0x0001]
mww $pll_ctrl_addr $pll_ctrl
echo "step set PLLEN BIT0 enable PLL"
mdw $pll_ctrl_addr
}
proc pll1_setup {pll_addr mult} {
mdw 0x01E1A000
#############################################################
# PLLC1 init
set pll_ctrl_addr [expr $pll_addr + 0x100]
set pll_ctrl [mrw $pll_ctrl_addr]
mdw $pll_ctrl_addr
#############################################################
# 1 - clear PLLENSRC (bit 5) for This bit must be cleared before the PLLEN bit will have any effect
set pll_ctrl [expr $pll_ctrl & ~0x0020]
mww $pll_ctrl_addr $pll_ctrl
echo "clear PLLENSRC BIT5"
mdw $pll_ctrl_addr
#############################################################
# 2 - clear PLLEN (bit 0) ... enter bypass mode
set pll_ctrl [expr $pll_ctrl & ~0x0001]
mww $pll_ctrl_addr $pll_ctrl
echo "clear PLLEN BIT0"
mdw $pll_ctrl_addr
#############################################################
# 3 - wait at least 4 refclk cycles
sleep 1
#############################################################
# 4 - clear PLLRST (bit 3) for PLL0 reset is asserted
set pll_ctrl [expr $pll_ctrl & ~0x0008]
mww $pll_ctrl_addr $pll_ctrl
echo "clear PLLRST BIT3 for reset"
mdw $pll_ctrl_addr
#############################################################
# 6 - clear PLLPWRDN (bit 1) for PLL0 is operating
set pll_ctrl [expr $pll_ctrl & ~0x0002]
mww $pll_ctrl_addr $pll_ctrl
echo "clear PLLPWRDN BIT1 for powerup"
mdw $pll_ctrl_addr
#############################################################
# 8 - optional: write pllm
mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xFF]
echo "set PLLM"
mdw [expr $pll_addr + 0x0110]
#############################################################
# 9 optional: write postdiv
set div [expr 0x8000 | 1]
mww [expr $pll_addr + 0x0128] $div
echo "set postdiv"
mdw [expr $pll_addr + 0x0128]
mww [expr $pll_addr + 0x0118] 0x8000
mww [expr $pll_addr + 0x011C] 0x8001
mww [expr $pll_addr + 0x0120] 0x8002
mdw [expr $pll_addr + 0x0118]
mdw [expr $pll_addr + 0x011C]
mdw [expr $pll_addr + 0x0120]
#############################################################
# set CMD go
mww [expr $pll_addr + 0x0138] 0x01
sleep 8
echo "set CDM go end"
mdw [expr $pll_addr + 0x0138]
#############################################################
# 10 - wait at least 5 usec for reset to finish
sleep 1
#############################################################
# 11 - set PLLRST BIT3
set pll_ctrl [expr $pll_ctrl | 0x0008]
mww $pll_ctrl_addr $pll_ctrl
echo "set PLLPWRDN BIT3 for exit reset"
mdw $pll_ctrl_addr
#############################################################
# 13 - wait at least 8000 refclk cycles for PLL to lock
sleep 800
#############################################################
# 14 - set PLLEN BIT0 ... leave bypass mode
set pll_ctrl [expr $pll_ctrl | 0x0001]
mww $pll_ctrl_addr $pll_ctrl
echo "set PLLEN bit0"
mdw $pll_ctrl_addr
#############################################################
# 14 OBSCLK enable
mww [expr $pll_addr + 0x0148] 0x2
}
proc am1808_init {} {
global AM1808
echo "Initialize AM1808 board"
set sysconfig_addr 0x01C14000
#############################################################
# unlock sysconfig
mww [expr $sysconfig_addr + 0x038] 0x83E70B13
mww [expr $sysconfig_addr + 0x03C] 0x95A4F1E0
#############################################################
# setup the CLKOUT pin
set pinmux13 [mrw [expr $sysconfig_addr + 0x154]]
set pinmux13 [expr $pinmux13 &~(0xF<<0x4)]
set pinmux13 [expr $pinmux13 | (0x1<<0x4)]
mww [expr $sysconfig_addr + 0x154] $pinmux13
mdw [expr $sysconfig_addr + 0x154]
#############################################################
# PLLC0 OBSCLK for PLL1C
set pll0_base_addr 0x01C11000
mww [expr $pll0_base_addr + 0x0104] 0x1E
echo "set PLL0 OBSCLK for"
mdw [expr $pll0_base_addr + 0x0104]
#############################################################
# unclok PLLC1
set sysconfig_cfg3 [mrw [expr $sysconfig_addr + 0x188]]
set sysconfig_cfg3 [expr $sysconfig_cfg3 & ~0x20]
mww [expr $sysconfig_addr + 0x188] $sysconfig_cfg3
mdw [expr $sysconfig_addr + 0x188]
#############################################################
# init PLLC1
set addr [dict get $AM1808 pllc2]
pll1_setup $addr 25
#############################################################
# unclok PLLC0
set sysconfig_cfg0 [mrw [expr $sysconfig_addr + 0x17C]]
set sysconfig_cfg0 [expr $sysconfig_cfg0 & ~0x10]
mww [expr $sysconfig_addr + 0x17C] $sysconfig_cfg0
mdw [expr $sysconfig_addr + 0x17C]
#############################################################
# init PLLC0
set addr [dict get $AM1808 pllc1]
pll0_setup $addr 25
#############################################################
# PLLC0 OBSCLK for PLL1C
set pll1_base_addr 0x01E1A000
mww [expr $pll1_base_addr + 0x0104] 0x19
mdw [expr $pll1_base_addr + 0x0104]
}
proc gdb { } {
jtag_reset 0 1
sleep 2
jtag_reset 0 0
halt
wait_halt
am1808_init
reg pc 0x80002000
}
