使用c6678开发平台；
Blackhawk XDS560v2-USB Mezzanine Emulator仿真器；
CCS: 5.2.1.00018；
仿真器相关配置如下：
测试连接的时候打印错误日志如下，麻烦帮忙分析一下，好多谢！
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\DOCUME~1\ADMINI~1\LOCALS~1\APPLIC~1\.TI\
213602635\0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 560/2xx-class product.
This utility will load the program 'bh560v2u.out'.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Aug 30 2012'.
The library build time was '22:16:38'.
The library package version is '5.0.838.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
An error occurred while hard opening the controller.
-----[An error has occurred and this utility has aborted]--------------------
This error is generated by TI's USCIF driver or utilities.
The value is '-233' (0xffffff17).
The title is 'SC_ERR_PATH_BROKEN'.
The explanation is:
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken
with a stuck-at-ones or stuck-at-zero fault.
[End]
Andy Yin1，您好：
之前是一直用可以连接仿真器的，连接方法是用BiosMulticoreSDK_2.1_GettingStartedGuide.pdf讲述的方法：
而上述打印信息是我点击Test Configuration 测试连接的打印信息：
在Test Configuration测试连接的时候还有可能打印消息如下：
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\DOCUME~1\ADMINI~1\LOCALS~1\APPLIC~1\.TI\
213602635\0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 560/2xx-class product.
This utility will load the program 'bh560v2u.out'.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Aug 30 2012'.
The library build time was '22:16:38'.
The library package version is '5.0.838.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
An error occurred while hard opening the controller.
-----[An error has occurred and this utility has aborted]--------------------
This error is generated by TI's USCIF driver or utilities.
The value is '-230' (0xffffff1a).
The title is 'SC_ERR_PATH_MEASURE'.
The explanation is:
The measured lengths of the JTAG IR and DR scan-paths are invalid.
This indicates that an error exists in the link-delay or scan-path.
[End]
