请问有没有MCBSP使用多通道传输的例程？我想配置发送端选择两个通道，两个接收端分别接收其中一个通道，这样配置对么？
#define MASTER
//#define SLAVER_1
//#define SLAVER_2
//extern void contrast_stretch(unsigned char *pin,unsigned char *pout,int N);
void Configure_DSK(void);
void Configure_MCBSP(void);
MCBSP_Handle DSK6416_MCBSPHANDLE;
void main(void) {
Uint32 i=5;
Uint32 j=5;
Uint32 cb;
CSL_init();
DSK6416_init();
DSK6416_LED_init();
DSK6416_DIP_init();
Configure_DSK();
#ifdef MASTER
while(1){
for(i=0;i<4;i++){
for(j=0;j<1000;j++);
while(!MCBSP_xrdy(DSK6416_MCBSPHANDLE));
if(!DSK6416_DIP_get(i)){
DSK6416_LED_init();
DSK6416_LED_on(i);
cb=MCBSP_FGET(MCR0,XCBLK);
MCBSP_write(DSK6416_MCBSPHANDLE,(i+2)&(0x3));
//cb=MCBSP_MCR0_FGET(XCBLK);
cb=MCBSP_FGET(MCR0,XCBLK);
cb=MCBSP_FGET(MCR0,XPABLK);
cb=MCBSP_FGET(MCR0,XPBBLK);
//for(j=0;j<1000;j++);
while(!MCBSP_xrdy(DSK6416_MCBSPHANDLE));
cb=MCBSP_FGET(MCR0,XCBLK);
MCBSP_write(DSK6416_MCBSPHANDLE,(i+3)&(0x3));
cb=MCBSP_FGET(MCR0,XCBLK);
cb=MCBSP_FGET(MCR0,XPABLK);
cb=MCBSP_FGET(MCR0,XPBBLK);
}
}
}
#endif
#ifdef SLAVER_1
while(1){
for(j=0;j<1000;j++);
while(!MCBSP_rrdy(DSK6416_MCBSPHANDLE));
i=MCBSP_read(DSK6416_MCBSPHANDLE);
DSK6416_LED_init();
DSK6416_LED_on(i);
}
#endif
#ifdef SLAVER_2
while(1){
for(j=0;j<1000;j++);
while(!MCBSP_rrdy(DSK6416_MCBSPHANDLE));
i=MCBSP_read(DSK6416_MCBSPHANDLE);
DSK6416_LED_init();
DSK6416_LED_on(i);
}
#endif
// MCBSP_write(DSK6416_MCBSPHANDLE,i);
// while(!MCBSP_rrdy(DSK6416_MCBSPHANDLE));
// o=MCBSP_read(DSK6416_MCBSPHANDLE);
// if(o!=i)
// ++e;
}
void Configure_DSK(void){
IRQ_globalDisable();
Configure_MCBSP();
IRQ_globalEnable();
}
void Configure_MCBSP(void){
MCBSP_Config mcbspCfgData = {
MCBSP_FMKS(SPCR, FREE, YES) |
MCBSP_FMKS(SPCR, SOFT, YES) |
MCBSP_FMKS(SPCR, FRST, YES) |
MCBSP_FMKS(SPCR, GRST, YES) |
MCBSP_FMKS(SPCR, XINTM, XRDY) |
MCBSP_FMKS(SPCR, XSYNCERR, NO) |
MCBSP_FMKS(SPCR, XRST, YES) |
MCBSP_FMKS(SPCR, DLB, OFF) | //
MCBSP_FMKS(SPCR, RJUST, RZF) |
MCBSP_FMKS(SPCR, CLKSTP, DISABLE) |
MCBSP_FMKS(SPCR, DXENA, OFF) |
MCBSP_FMKS(SPCR, RINTM, RRDY) |
MCBSP_FMKS(SPCR, RSYNCERR, NO) |
MCBSP_FMKS(SPCR, RRST, YES),
MCBSP_FMKS(RCR, RPHASE, SINGLE) |
MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RCOMPAND, MSB) | //MSB first
MCBSP_FMKS(RCR, RFIG, YES) |
MCBSP_FMKS(RCR, RDATDLY, 0BIT) |
MCBSP_FMKS(RCR, RFRLEN1, OF(127)) | //4 words per frame
MCBSP_FMKS(RCR, RWDLEN1, 8BIT) | //8 bits per word
MCBSP_FMKS(RCR, RWDREVRS, DISABLE),
MCBSP_FMKS(XCR, XPHASE, SINGLE) |
MCBSP_FMKS(XCR, XFRLEN2, DEFAULT) |
MCBSP_FMKS(XCR, XWDLEN2, DEFAULT) |
MCBSP_FMKS(XCR, XCOMPAND, MSB) |
MCBSP_FMKS(XCR, XFIG, YES) |
MCBSP_FMKS(XCR, XDATDLY, 0BIT) |
MCBSP_FMKS(XCR, XFRLEN1, OF(127)) |
MCBSP_FMKS(XCR, XWDLEN1, 8BIT) |
MCBSP_FMKS(XCR, XWDREVRS, DISABLE),
MCBSP_FMKS(SRGR, GSYNC, FREE) |
MCBSP_FMKS(SRGR, CLKSP, RISING) | //rising edge of CLKS generates CLKG and FSG
MCBSP_FMKS(SRGR, CLKSM, INTERNAL) | //generator derived from cpu clock (250M)
MCBSP_FMKS(SRGR, FSGM, FSG) | //FSX is generated on every DXR-to-XSR copy.ignore the next two register
MCBSP_FMKS(SRGR, FPER, OF(1023)) |
MCBSP_FMKS(SRGR, FWID, OF(2)) |
MCBSP_FMKS(SRGR, CLKGDV, OF(25)), //25 clk divided
MCBSP_FMKS(MCR, XMCME, NORMAL) |
MCBSP_FMKS(MCR, XPBBLK, SF1) |
MCBSP_FMKS(MCR, XPABLK, SF0) |
MCBSP_FMKS(MCR, XMCM, DISXP) |
MCBSP_FMKS(MCR, RMCME, NORMAL) |
MCBSP_FMKS(MCR, RPBBLK, SF1) |
MCBSP_FMKS(MCR, RPABLK, SF0) |
MCBSP_FMKS(MCR, RMCM, ELDISABLE),
#ifdef MASTER
MCBSP_FMKS(RCERE0, RCE, OF(0x00000010)),
#endif
#ifdef SLAVER_1
MCBSP_FMKS(RCERE0, RCE, OF(0x00000002)),
#endif
#ifdef SLAVER_2
MCBSP_FMKS(RCERE0, RCE, OF(0x00000008)),
#endif
MCBSP_RCERE1_DEFAULT,
MCBSP_RCERE2_DEFAULT,
MCBSP_RCERE3_DEFAULT,
#ifdef MASTER
MCBSP_FMKS(XCERE0, XCE, OF(0x00000010)),
#endif
#ifdef SLAVER_1
MCBSP_FMKS(XCERE0, XCE, OF(0x00000002)),
#endif
#ifdef SLAVER_2
MCBSP_FMKS(XCERE0, XCE, OF(0x00000008)),
#endif
MCBSP_XCERE1_DEFAULT,
MCBSP_XCERE2_DEFAULT,
MCBSP_XCERE3_DEFAULT,
MCBSP_FMKS(PCR, XIOEN, SP) |
MCBSP_FMKS(PCR, RIOEN, SP) |
MCBSP_FMKS(PCR, FSXM, INTERNAL) |
MCBSP_FMKS(PCR, FSRM, EXTERNAL) |
MCBSP_FMKS(PCR, CLKXM, OUTPUT) |
MCBSP_FMKS(PCR, CLKRM, INPUT) |
MCBSP_FMKS(PCR, CLKSSTAT, 0) |
MCBSP_FMKS(PCR, DXSTAT, 0) |
MCBSP_FMKS(PCR, FSXP, ACTIVEHIGH) |
MCBSP_FMKS(PCR, FSRP, ACTIVEHIGH) |
MCBSP_FMKS(PCR, CLKXP, RISING) |
MCBSP_FMKS(PCR, CLKRP, FALLING)
};
/* Open codec data handle */
DSK6416_MCBSPHANDLE = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);
//if (DSK6416_AIC23_DATAHANDLE == INV)
// return (DSK6416_AIC23_CodecHandle)INV;
/* Configure codec data McBSP */
MCBSP_config(DSK6416_MCBSPHANDLE, &mcbspCfgData);
/* Clear any garbage from the codec data port */
if (MCBSP_rrdy(DSK6416_MCBSPHANDLE))
MCBSP_read(DSK6416_MCBSPHANDLE);
/* Start McBSP0 as the codec data channel */
MCBSP_start(DSK6416_MCBSPHANDLE, MCBSP_XMIT_START | MCBSP_RCV_START |
MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, MCBSP_SRGR_DEFAULT_DELAY);
}