shareRegion的isValid字段 只有前两个设为true时能attach通过。后面三个设为true时就会出现Attach host出错。
SharedRegion.numEntries = 5;
SharedRegion.setEntryMeta( 0,
{
base: sr0MemSection.base,
len: sr0MemSection.len,
name: sr0MemSection.name,
isValid: true,
ownerProcId: srOwnerProcId,
cacheEnable: false,
cacheLineSize: 128,
createHeap: true
}
);
/*
This section is mainly used for bitstream buffer's
which need to be cached on A8 side for better performance
of HDD, ethernet read/write
A8 - CACHED
M3 - CACHED
DSP - CACHED
*/
SharedRegion.setEntryMeta( 1,
{
base: sr1MemSection.base,
len: sr1MemSection.len,
name: sr1MemSection.name,
isValid: true,
ownerProcId: srOwnerProcId,
cacheEnable: true,
cacheLineSize: 128,
createHeap: true
}
);
/*
This section is used for video frame buffers
Since M3's doesnt directly access video frame buffers,
we dont need to do cache operations in this section
hence it marked as NON-CACHED.
A8 - NOT CACHED
M3 - NOT CACHED
DSP - NOT CACHED
*/
SharedRegion.setEntryMeta( 2,
{
base: sr2MemSection.base,
len: sr2MemSection.len,
name: sr2MemSection.name,
isValid: false,
ownerProcId: srFrmBufferOwnerProcId,
cacheEnable: /*true,*/true,
cacheLineSize: 128,
createHeap: true
}
);
/*
This section is used for ipc control structures for intra ducati communication
A8 - NOT PRESENT
M3 - CACHED but no cache coherency done
DSP - NOT PRESENT
*/
SharedRegion.setEntryMeta( 3,
{
base: sr3MemSection.base,
len: sr3MemSection.len,
name: sr3MemSection.name,
isValid: false,
ownerProcId: srFrmBufferOwnerProcId,
cacheEnable: true,
cacheLineSize: 128,
createHeap: true
}
);
SharedRegion.setEntryMeta( 4,
{
base: sr4MemSection.base,
len: sr4MemSection.len,
name: sr4MemSection.name,
isValid: false,
ownerProcId: srFrmBufferOwnerProcId,
cacheEnable: true,
cacheLineSize: 128,
createHeap: true
}
);