8位并行数据输入， 帧有效和行有效都是输入的。
数据流 sensor --》 CCDC --》 memory
现在是在一份接收bt656格式的驱动上改的， 把跟场相关和bt656相关的都去掉了，
以下是具体寄存器的配置
ISP_SYSCONFIG:
MIDLE_MODE =No-standby:
AUTO_IDLE = 0x1: Automatic clock gating strategy
-----------------------------------------------------------------------------------
ISP_CTRL:
ISPCTRL_CCDC_CLK_EN
ISPCTRL_CCDC_RAM_EN
ISPCTRL_RSZ_CLK_EN
SYNC_DETECT==0x2: VS falling edge
SHIFT = 0x3: Shift by 6 CAMEXT[13:6] - CAM [7:0]
|ISPCTRL_CCDC_FLUSH
|ISPCTRL_SBL_WR0_RAM_EN
|ISPCTRL_SBL_WR1_RAM_EN
|ISPCTRL_SBL_RD_RAM_EN
PAR_BRIDGE = 0x3: The bridge is enabled. The first byte is written toCAM.DATA[15:8], the second byte is written toCAM.DATA[7:0]
PAR_SER_CLK_SEL= 0x0: Selects the 12-bit parallel interface as the input tothe CCDC module.
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IRQ0ENABLE :
IRQ0STATUS_HS_VS_IRQ |
IRQ0STATUS_RSZ_DONE_IRQ |
IRQ0STATUS_CCDC_VD0_IRQ |
IRQ0STATUS_CCDC_VD1_IRQ;
----------------------------------
CCDC_CFG:
VDLC == 0x1: Not latched on VS
-------------------------------------------------------
CCDC_SYN_MODE
17 WEN ==1 Data write enable.
16 VDHDEN = 0x1: Enable;
13:12 INPMOD = 0x1: YCbCr data on 16 bits. It is required to enable the 8to 16-bit bridge in the ISP_CTRL register.
10:8 DATSIZ = 0x0: cam_d is 8 bits but the 8 to 16-bit bridge is enabled in the ISP_CTRL register.
7 FLDMODE = 0 progressive
0 VDHDOUT = 0 input;
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CCDC_SDR_ADDR is also configed.
--------------------------------
CCDC_HORZ_INFO:
30:16 SPH Start pixel horizontal: 0
14:0 NPH Number of pixels horizontal: 480 - 1;
---------------------------------
CCDC_VERT_LINES:
14:0 NLV Number of lines - vertical direction: 640 - 1
-----------------
CCDC_VDINT也设置了，但是只有等于0的时候才会有VD0_IRQ中断产生， 不知道是什么原因
以上有哪设置错了么？ 或者还有那个寄存器没有设置么？
