If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
The EMIFB requires two input clocks to source VCLK and MCLK (see Figure 7-3): • VCLK is sourced from SYSCLK2 that clocks the peripheral bus interface of EMIFB • MCLK, which sets the clock rate for the I/O clock (EMB_CLK), is sourced from either SYSCLK5 or DIV4P5. The EMB_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module controls whether SYSCLK5 or DIV4P5 is selected as the clock source for MCLK.
