DM8127的DDR3芯片

确认一下DDR颗粒的手册，是否时序参数有变化，最好把DDR3的leveling重新做一下，另外可以先试试仿真器能不能连上。

DDR leveling的链接： http://processors.wiki.ti.com/index.php?title=TI814x-DDR3-Init-U-Boot&redirect=no

您好，Louis。

按您的提议，

这是我从板子上运行

DDR3_SlaveRatio_ByteWiseSearch_TI814x.out后得到的结果

Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
0
DDR START ADDR=0x80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
0xa5

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
0x34

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0x13
Enter the input file Name
Ti814x_Ratio_values
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
WR DATA RATIO MAXIMUM VALUE DIDN'T CONVERGE
WR DATA RATIO MINIMUM VALUE DIDN'T CONVERGE
*********************************************************
Byte level Slave Ratio Search Program Values
*********************************************************
BYTE3 BYTE2 BYTE1 BYTE0
*********************************************************
Read DQS MAX 0 20000007 0 0
Read DQS MIN 33 0 0 0
Read DQS OPT 80000019 10000003 0 0
*********************************************************
Read DQS GATE MAX 0 0 0 0
Read DQS GATE MIN 0 0 0 0
Read DQS GATE OPT 0 0 0 0
*********************************************************
Write DQS MAX 0 14 0 0
Write DQS MIN 0 0 0 0
Write DQS OPT 0 a 0 0
*********************************************************
Write DATA MAX 0 0 0 0
Write DATA MIN 0 0 0 0
Write DATA OPT 0 0 0 0
*********************************************************

===== END OF TEST =====

这个很不好理解。

刚才百度了一下，看到有人提到说MT41J和MT41K的初起不一样，不知道初起是指的什么，在ti814x ddr3的文件里怎么调。

你仔细对比一下J和K的时序参数看看是不是完全一样的。

时序参数不同的话对DDR时序的配置就是不同的。 Leveling是在时序配置的前提下进一步优化稳定性的手段。

你的打印指出DDR leveling不能收敛，可能是xls里面的配置有误导致seed初始值不正确，或者DDR时序寄存器不对导致。

再者， 请问你的情形是全部参数不能收敛，还是部分参数不能。

如果是后者，请用收敛完毕的参数替代为新的seed填入，重新leveling，这样可能可以进一步帮助收敛其他的值。