TI专家、各位朋友:
http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf Figure 32-2. UART Clock Generation Diagram
问:分别对于UART0 UART1 UART2上图中的Input clock分别是哪个?
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TI专家、各位朋友:
http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf Figure 32-2. UART Clock Generation Diagram
问:分别对于UART0 UART1 UART2上图中的Input clock分别是哪个?
在OMAP-L138数据手册第195页UART时序图下面的注释里有说明。
http://www.ti.com/lit/ds/symlink/omap-l138.pdf
For UART0, the UART input clock is SYSCLK2.
For UART1 or UART2, the UART input clock is ASYNC3 (either PLL0_SYCLK2 or PLL1_SYSCLK2).