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自己开发的板卡，V6FPGA通过SRIO向DSPDSP外挂的DDR3中写数据，乒乓结构。当FPGA往乒写数据时，DSP会处理乓中的数据。现在问题是，当FPGA和DSP同时访问DDR时，访问优先级可以设置吗，哪个手册上面有相关的介绍，谢谢
可以设置。
SRIO的设置寄存器为：srioRegs->RIO_PER_SET_CNTL
DSP核对设置寄存器为:CGEM_regs->MDMAARBU, XMC_regs->MDMAARBX
FPGA通过SRIO访问DDR的优先级由SRIO的RIO_PER_SET_CNTL寄存器控制，请参阅SRIO user guide。
DSP和访问DDR的优先级有MDMAARBU和MDMAARBX寄存器控制，请参阅TMS320C66x CorePac User's Guide.
多谢指点
