硬件：c6678
// The System PLL governs the device (CorePac) operating speed.
//
// Each board designer defines the CLKIN frequency. On the
// TMDXEVM6678L,LE,LXE EVMs, the CLKIN frequency defined to 100MHz. The
// values for PLL1_M(39) and PLL1_D(1) defined below are pre-set
// to provide a 1000MHz operating frequency on the EVMs.
//
// Other board designs using different CLKIN frequencies and/or
// applications that requiring other operating frequecies, the PLL can
// be configured by adjusting PLL1_M and PLL1_D per the
// following formula:
//
// Target Frequency (MHz) =
// input_clock (MHz) * [(PLL1_M + 1)]/ (2 * (PLL1_D + 1) )
//
// Table 2-13, "C66x DSP System PLL Configuration" in the device data sheet,
// focus.ti.com/.../tms320c6678.pdf provides the suggested
// values for PLL1_M and PLL1_D for various input clocks and desired
// operating frequencies.
//
// Please note that there might be multiple PLL1_M and PLL1_D
// values for the same Input clock and Desired Device Speed as long as the
// multipliers and dividers are in the acceptable range.
//
// More details on the PLL including the limitations on acceptable ranges
// for multipliers and dividers are in the PLL's user guide at
// http://www.ti.com/lit/sprugv2
//
// The table provides some sample values of PLL1_M and PLL1_D:
//
// Please select PLL1_M values such that 0 < PLL1_M <= 64
// +--------------------+---------------+--------+--------+
// | (CLK)Desired | (CLKIN) Input | | |
// | Device Speed (MHz) | Clock (MHz) | PLL1_M | PLL1_D |
// +--------------------+---------------+--------+--------+
// | 1000 | 100 | 19 | 0 |
// | 1000 | 100 (EVM) | 39 | 1 |
// | 1250 | 100 | 24 | 0 |
// | 1000 | 50 | 39 | 1 |
// | 1000 | 156.25 | 63 | 4 |
// +--------------------+---------------+--------+--------+
//
// +--------------------+---------------+--------+--------+
// | PA PLL VCO | (CLKIN) Input | | |
// | Rate (MHz) | Clock (MHz) | PLL1_M | PLL1_D |
// +--------------------+---------------+--------+--------+
// | 1050 | 100.00 (EVM) | 20 | 0 |
// | 1044 | 122.88 | 31 | 1 |
// | 1050 | 122.88 | 204 | 11 |
// | 1050 | 156.25 | 335 | 24 |
// +--------------------+---------------+--------+--------+
//
// +--------------------+---------------+--------+--------+
// | DDR3 PLL VCO | (CLKIN) Input | | |
// | Rate (MHz) | Clock (MHz) | PLL1_M | PLL1_D |
// +--------------------+---------------+--------+--------+
// | 1333 | 66.667 (EVM) | 19 | 0 |
// | 1066 | 66.667 | 31 | 1 |
// | 800 | 66.667 | 11 | 0 |
// +--------------------+---------------+--------+--------+
第三张表的第一行是怎么算出来的，好像不是使用上述的公式算出，那是按照什么公式来的？
