问题描述如下：
CCS版本：5.2.1；
BIOS-MCSDK版本：2.1.2.5；
硬件平台：TMDXEVM6678L；
在平台上跑C:\ti\dsplib_c66x_3_1_0_0\packages\ti\dsplib\src\DSPF_sp_fftSPxSP\c66下的DSPF_sp_fftSPxSP_66_LE_COFF工程的时候：
将DSPF_sp_fftSPxSP_d.c里的
#define MAXN (1024)改为#define MAXN (4096)，主要测试4096点的FFT时间
最后跑出来的结果如下：
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 1 Intrinsic Successful SA Successful N = 8 radix = 2 natC: 2987 optC: 1258 SA: 449
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 2 Intrinsic Successful SA Successful N = 16 radix = 4 natC: 4548 optC: 2445 SA: 891
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 3 Intrinsic Successful SA Successful N = 32 radix = 2 natC: 12216 optC: 6759 SA: 2391
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 4 Intrinsic Successful SA Successful N = 64 radix = 4 natC: 22250 optC: 14073 SA: 4986
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 5 Intrinsic Successful SA Successful N = 128 radix = 2 natC: 60030 optC: 36207 SA: 12692
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 6 Intrinsic Successful SA Successful N = 256 radix = 4 natC: 114827 optC: 75448 SA: 26646
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 7 Intrinsic Successful SA Successful N = 512 radix = 2 natC: 294752 optC: 183213 SA: 64692
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 8 Intrinsic Successful SA Successful N = 1024 radix = 4 natC: 571425 optC: 380294 SA: 134638
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 9 Intrinsic Successful SA Successful N = 2048 radix = 2 natC: 1406626 optC: 891049 SA: 315550
[C66xx_0] DSPF_sp_fftSPxSP Iter#: 10 Intrinsic Successful SA Successful N = 4096 radix = 4 natC: 2753235 optC: 1846748 SA: 659716
[C66xx_0] Memory: 1184 bytes
[C66xx_0] Cycles: 12692 (N=128) 26646 (N=256)
EVM板的主频时钟为1G，这样算下来4096点FFT经过优化的optC时间为：1846748/1000000000 = 1.846748ms，感觉这个时间也太长了，不知道是我算的问题还是其他的问题！！
求专家给解答一下啊！！！！
Gel文件初始化如下：
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: C6678L GEL file Ver is 2.005
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ...
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Passed
C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ...
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output:
SGMII SERDES has been configured.
C66xx_0: GEL Output: Enabling EDC ...
C66xx_0: GEL Output: L1P error detection logic is enabled.
C66xx_0: GEL Output: L2 error detection/correction logic is enabled.
C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_0: GEL Output: Enabling EDC ...Done
C66xx_0: GEL Output: Configuring CPSW ...
C66xx_0: GEL Output: Configuring CPSW ...Done
C66xx_0: GEL Output: Global Default Setup... Done.
