This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Keystone2_DDR3_Spreadsheet

管理员,k2的DDR3_Spreadsheet给个包,之前下的k1的是2012版本的貌似不适用

  • 如附件,结合KII STK DDR初始化函数进行配置。

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/383853/1363161

    KII STK: http://www.deyisupport.com/question_answer/dsp_arm/c6000_multicore/f/53/t/74528.aspx

    K2 DDR3 Register Calc v1p51.xlsx
  • 关于DDR3 PHY Calc有没有K2版本的?还是说K1和k2通用:DDR3 PHY Calc v10.xlsx

  • K2只需要附件的表格计算PHY及controller寄存器,之前K1的PHY Calc spreadsheet是用于计算leveling 参数,现在不需要了,关于DDR的配置具体参考gel及STK

  • C66xx_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x150: (Error -1178 @ 0x80000000) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)

    在配置了寄存器后···初始化DDR能通过,但是访问0x80000000  DDRA的地址就出错了,报错如上。

    PLL配置没有问题,内存电压和输入时钟都正确····无论有没有内存条访问这个地址都是报这个错。请问这是什么情况?

  • 你是基于K2 STK中的DDR初始化代码修改测试的么,其中在DDR初始之后有对DDR进行测试的。

    KII STK: http://www.deyisupport.com/question_answer/dsp_arm/c6000_multicore/f/53/t/74528.aspx

  • 不是修改k2 STK的代码·····

    1:在gel文件修改的,加载gel,初始化后,访问0x60000000就出错

    2:修改D:\ti\pdk_keystone2_3_01_01_04\packages\ti\platform\evmk2h这个项目的evmc66x.c的·······生成的ti.platform.evmk2h.lite.lib在POST中使用,

    在运行过程中,ddrA,B初始化都过了,暂停运行,然后访问0x60000000也出错

    错误都是C66xx_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x150: (Error -1178 @ 0x80000000) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)

    这个情况是怎么回事??

  • Andy Yin1:

    我更换了一个内存条,在k2的STK修改memory_test的相关PLL。

    在DDR3A初始化完成时,Console如下:

    [C66xx_0] Initialize DSP main clock = 156.25MHz/3x11 = 572MHz
    DDR3A initialization
    Initialize DDR data rate = 156.250x13/3= 677.1 MTS
    wait DDR3 PHY status in PGSR0 register timeout!
    DDR PHY status PGSR0=0x810001ff.
    DDR PHY Write Bit Deskew is NOT done!
    DDR PHY Read Eye Training is NOT done!
    DDR PHY Write Eye Training is NOT done!

    这时memory browser访问0x800000000时能够正常读写,后续TEST能通过部分

    问题:DDR PHY Write Bit Deskew is NOT done!
    DDR PHY Read Eye Training is NOT done!
    DDR PHY Write Eye Training is NOT done!

    这三个问题怎么解?