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使用外部同步事件int1触发dma中断,第一次可以进得去,第二次就进不去

5509a和fifo连接,用emif端口从fifo中读取数据,dma把数据从emif端口搬到内存,每次搬运完1帧产生dma中断,但是第一次中断能正常进入,第二次中断只能读取几个数据(未满一帧),不能进入中断


#include <csl.h>
#include <csl_irq.h>

#include <csl_dma.h>
#include <csl_pll.h>
#include <csl_emif.h>
#include <csl_chip.h>
#include <stdio.h>
#include <_csl_pgpio.h>
#include <csl_gpio.h>
#include "port5509Adma.h"
#define N 4096

 

int *souraddr,temp;
Uint16 eventId0;
int old_intm,i;

#pragma DATA_SECTION(databuffer,"dmaMem")
unsigned int databuffer[4096],sj[4096];
#pragma DATA_SECTION(src,"shuju")
unsigned int src[4096];

//interrupt void int1(void);
interrupt void dma1_int();
//---------Function prototypes---------

/* Reference start of interrupt vector table   */

/* This symbol is defined in file, vectors_IP.s55 */

extern void VECSTART(void);
void  taskFxn(void);

/*锁相环的设置*/
PLL_Config  myConfig      = {
  0,    //IAI: the PLL locks using the same process that was underway
                //before the idle mode was entered
  1,    //IOB: If the PLL indicates a break in the phase lock,
                //it switches to its bypass mode and restarts the PLL phase-locking
                //sequence
  24,    //PLL multiply value; multiply 12 times
  1             //Divide by 2 PLL divide value; it can be either PLL divide value
                //(when PLL is enabled), or Bypass-mode divide value
                //(PLL in bypass mode, if PLL multiply value is set to 1)
};

EMIF_Config emiffig = {
  0x221,  //EGCR  : the MEMFREQ = 00,the clock for the memory is equal to cpu frequence
     //    the WPE = 0 ,forbiden the writing posting when we debug the EMIF
     //        the MEMCEN = 1,the memory clock is reflected on the CLKMEM pin
     //        the NOHOLD = 1,HOLD requests are not recognized by the EMIF
  0xFFFF, //EMI_RST: any write to this register resets the EMIF state machine
  0x1fff, //CE0_1:  CE0 space control register 1
     //        MTYPE = 011,Synchronous DRAM(SDRAM),16-bit data bus width
  0xFFFF,   //CE0_2:  CE0 space control register 2
  0x00FF,   //CE0_3:  CE0 space control register 3
     //        TIMEOUT = 0xFF;
  0x1112, //CE1_1:  CE0 space control register 1
            //        Asynchronous, 16Bit
  0x0fff, //CE1_2:  CE0 space control register 2
  0x000F, //CE1_3:  CE0 space control register 3
 
  0x1FFF, //CE2_1:  CE0 space control register 1
            //        Asynchronous, 16Bit
  0xFFFF, //CE2_2:  CE0 space control register 2
  0x00FF, //CE2_3:  CE0 space control register 3
 
  0x1FFF, //CE3_1:  CE0 space control register 1
            //        Asynchronous, 16Bit
  0xFFFF, //CE3_2:  CE0 space control register 2
  0x00FF, //CE3_3:  CE0 space control register 3
 
  0x2911,   //SDC1:   SDRAM control register 1
     //    TRC = 8
     //        SDSIZE = 0;SDWID = 0
     //        RFEN = 1
     //        TRCD = 2
     //        TRP  = 2
  0x0410, //SDPER : SDRAM period register
     //    7ns *4096
  0x07FF,    //SDINIT: SDRAM initialization register
     //        any write to this register to init the all CE spaces,
     //        do it after hardware reset or power up the C55x device
  0x0131 //SDC2:   SDRAM control register 2
     //        SDACC = 0;
     //        TMRD = 01;
     //        TRAS = 0101;
     //        TACTV2ACTV = 0001;         
  };

void init_dma1(unsigned int * src_data,unsigned int * dst_data)
{
 unsigned long int tem;

 *DMA_CCR1=0x4370;
 
 *DMA_GCR=0x0008;
 *DMA_GSCR=0x0001;
 *DMA_GTCR=0x0000;

 *DMA_CICR1=0x0008;
 *DMA_CSDP1=0xc389;
 *DMA_CEN1=0x1000;
 *DMA_CFN1=0x0001;
 *DMA_CSEI1=0x0000;
 *DMA_CSFI1=0x0000;
 *DMA_CDEI1=0x0000;
 *DMA_CDFI1=0x0000;

 *DMA_CSSA_L1=(unsigned int)(src_data)<<1;
 tem=((unsigned long int)(src_data))>>15;
 *DMA_CSSA_U1=(unsigned int)(tem);

 *DMA_CDSA_L1=(unsigned int)(dst_data)<<1;
 tem=((unsigned int)(dst_data))>>15;
 *DMA_CDSA_U1=(unsigned int)(tem);


 *DMA_CCR1=0x43f0;

}

 

void delay()
{
 Uint32 j = 0,k = 0;
 for(j = 0;j<0x1;j++)
 {
  for(k= 0;k<0xff;k++)
  {}
 }
}

main()
{
 /*初始化CSL库*/ 
    CSL_init();
   
    /*EMIF为全EMIF接口*/
    CHIP_RSET(XBSR,0x0a01);
   
    /*设置系统的运行速度为144MHz*/
    PLL_config(&myConfig); 
 EMIF_config(&emiffig);
 
 taskFxn();
}
void  taskFxn(void)
{

    Uint16 eventId0;//定义中断ID号
 

   
    /* Set Interrupt Vector Start Location */
    IRQ_setVecs((Uint32)(&VECSTART));    
 /* Get Interrupt Event Id associated with this DMA */
    eventId0 = IRQ_EVT_DMAC1;
 
   
    /* Temporarily Disable All Interrupts */
    old_intm = IRQ_globalDisable();

 

    /* Enable the DMA interrupt in IER register */
    IRQ_enable(eventId0);

    /* Enable all maskable interrupts */  
    IRQ_globalEnable();                
  _PGPIO_pinEnable(GPIO_PIN6);
 _PGPIO_pinDirection(GPIO_PIN6,1);
 _PGPIO_pinWrite(GPIO_PIN6,1);
    delay();
 _PGPIO_pinWrite(GPIO_PIN6,0);
    delay();
 _PGPIO_pinWrite(GPIO_PIN6,1);
    delay();
 init_dma1(src,databuffer);

 /*实现连续采集数据--以帧为单位*/
 while(1)
 {; }

    
}


interrupt void dma1_int()
{
   

 temp= *(DMA_CSR1);
  

 for(i=0;i<4096;i++)
  sj[i]=databuffer[i];
 asm("");  
}


/******************************************************************************\
* End of pll2.c
\******************************************************************************/

  .sect ".vectors"
        .global _VECSTART


*------------------------------------------------------------------------------

* Global symbols referenced in this file but defined somewhere else.

* Remember that your interrupt service routines need to be referenced here.

*------------------------------------------------------------------------------

        
         .ref _c_int00           ; C entry point
     
   .ref _dma1_int
         ;.ref _flash
 
         .align  080h   ;must be aligned on page boundary
_VECSTART:            
        .ivec _c_int00,c54x_stk

nmi     .ivec no_isr
         nop_16
                            
int0    .ivec  no_isr
         nop_16
int2    .ivec  no_isr
         nop_16
tint0   .ivec  no_isr
         nop_16
rint0   .ivec  no_isr
         nop_16
rint1   .ivec  no_isr
         nop_16
xint1   .ivec  no_isr
         nop_16
usb     .ivec  no_isr
         nop_16
dmac1   .ivec  _dma1_int
         nop_16
dspint  .ivec  no_isr
         nop_16
int3    .ivec  no_isr
         nop_16
rint2   .ivec  no_isr
         nop_16
xint2   .ivec  no_isr
         nop_16
dmac4   .ivec  no_isr
         nop_16
dmac5   .ivec  no_isr
         nop_16                                                                                                                                                                                              
int1    .ivec  no_isr
         nop_16
xint0   .ivec  no_isr
         nop_16
dmac0   .ivec  no_isr
         nop_16
int4    .ivec  no_isr
         nop_16
dmac2   .ivec  no_isr
         nop_16
dmac3   .ivec  no_isr
         nop_16
tint1   .ivec  no_isr
         nop_16
iic     .ivec  no_isr
         nop_16
berr    .ivec  no_isr
         nop_16
dlog    .ivec  no_isr
         nop_16
rtos    .ivec  no_isr
         nop_16
iv27    .ivec  no_isr
         nop_16
iv28    .ivec  no_isr
         nop_16
iv29    .ivec  no_isr
         nop_16
siv30   .ivec  no_isr
         nop_16
siv31   .ivec  no_isr
         nop_16


        .text

        .def no_isr

no_isr:

        b #no_isr

  • /*
    ***************************************************
    *FILENAME:portdma.H                       *
    *This include file contains all addresses of    *
    *the registers of DMA in 5509a.                   *
    *BY:Zhuangyueqian       DATE:2005.12.13         * 
    ***************************************************
    */

    //**global address **
    #define     DMA_GCR     (volatile  int ioport *)   0x0E00      //DMA Global Control Register
    #define     DMA_GSCR    (volatile  int ioport *)   0x0E02      //DMA Software Compatibility Register
    #define     DMA_GTCR    (volatile  int ioport *)   0x0E03      //DMA Timeout Control Register

    //**dma0**
    #define     DMA_CSDP0   (volatile  int ioport *)   0x0C00      //DMA Channel 0 Source Destination
    #define     DMA_CCR0    (volatile  int ioport *)   0x0C01      //DMA Channel 0 Control Register
    #define     DMA_CICR0   (volatile  int ioport *)   0x0C02      //DMA Channel 0 Interrupt Control Register
    #define     DMA_CSR0    (volatile  int ioport *)   0x0C03      //DMA Channel 0 Status Register
    #define     DMA_CSSA_L0 (volatile  int ioport *)   0x0C04      //DMA Channel 0 Source Start Address Register(lower bits)
    #define     DMA_CSSA_U0 (volatile  int ioport *)   0x0C05      //DMA Channel 0 Source Start Address Register(upper bits)
    #define     DMA_CDSA_L0 (volatile  int ioport *)   0x0C06      //DMA Channel 0 Source Destination Address Register(lower bits)
    #define     DMA_CDSA_U0 (volatile  int ioport *)   0x0C07      //DMA Channel 0 Source Destination Address Register(upper bits)
    #define     DMA_CEN0    (volatile  int ioport *)   0x0C08      //DMA Channel 0 Element Number Register
    #define     DMA_CFN0    (volatile  int ioport *)   0x0C09      //DMA Channel 0 Frame Number Register
    #define     DMA_CSFI0   (volatile  int ioport *)   0x0C0A      //DMA Channel 0 Source Frame Index Register
    #define     DMA_CSEI0   (volatile  int ioport *)   0x0C0B      //DMA Channel 0 Source Element Index Register
    #define     DMA_CSAC0   (volatile  int ioport *)   0x0C0C      //DMA Channel 0 Source Address Counter
    #define     DMA_CDAC0   (volatile  int ioport *)   0x0C0D      //DMA Channel 0 Destination Address Counter
    #define     DMA_CDEI0   (volatile  int ioport *)   0x0C0E      //DMA Channel 0 Destination Element Index Register
    #define     DMA_CDFI0   (volatile  int ioport *)   0x0C0F      //DMA Channel 0 Destination Frame Index Register

    //**dma1**
    #define     DMA_CSDP1   (volatile  int ioport *)   0x0C20      //DMA Channel 1 Source Destination
    #define     DMA_CCR1    (volatile  int ioport *)   0x0C21      //DMA Channel 1 Control Register
    #define     DMA_CICR1   (volatile  int ioport *)   0x0C22      //DMA Channel 1 Interrupt Control Register
    #define     DMA_CSR1    (volatile  int ioport *)   0x0C23      //DMA Channel 1 Status Register
    #define     DMA_CSSA_L1 (volatile  int ioport *)   0x0C24      //DMA Channel 1 Source Start Address Register(lower bits)
    #define     DMA_CSSA_U1 (volatile  int ioport *)   0x0C25      //DMA Channel 1 Source Start Address Register(upper bits)
    #define     DMA_CDSA_L1 (volatile  int ioport *)   0x0C26      //DMA Channel 1 Source Destination Address Register(lower bits)
    #define     DMA_CDSA_U1 (volatile  int ioport *)   0x0C27      //DMA Channel 1 Source Destination Address Register(upper bits)
    #define     DMA_CEN1    (volatile  int ioport *)   0x0C28      //DMA Channel 1 Element Number Register
    #define     DMA_CFN1    (volatile  int ioport *)   0x0C29      //DMA Channel 1 Frame Number Register
    #define     DMA_CSFI1   (volatile  int ioport *)   0x0C2A      //DMA Channel 1 Source Frame Index Register
    #define     DMA_CSEI1   (volatile  int ioport *)   0x0C2B      //DMA Channel 1 Source Element Index Register
    #define     DMA_CSAC1   (volatile  int ioport *)   0x0C2C      //DMA Channel 1 Source Address Counter
    #define     DMA_CDAC1   (volatile  int ioport *)   0x0C2D      //DMA Channel 1 Destination Address Counter
    #define     DMA_CDEI1   (volatile  int ioport *)   0x0C2E      //DMA Channel 1 Destination Element Index Register
    #define     DMA_CDFI1   (volatile  int ioport *)   0x0C2F      //DMA Channel 1 Destination Frame Index Register

    //**dma2**
    #define     DMA_CSDP2   (volatile  int ioport *)   0x0C40      //DMA Channel 2 Source Destination
    #define     DMA_CCR2    (volatile  int ioport *)   0x0C41      //DMA Channel 2 Control Register
    #define     DMA_CICR2   (volatile  int ioport *)   0x0C42      //DMA Channel 2 Interrupt Control Register
    #define     DMA_CSR2    (volatile  int ioport *)   0x0C43      //DMA Channel 2 Status Register
    #define     DMA_CSSA_L2 (volatile  int ioport *)   0x0C44      //DMA Channel 2 Source Start Address Register(lower bits)
    #define     DMA_CSSA_U2 (volatile  int ioport *)   0x0C45      //DMA Channel 2 Source Start Address Register(upper bits)
    #define     DMA_CDSA_L2 (volatile  int ioport *)   0x0C46      //DMA Channel 2 Source Destination Address Register(lower bits)
    #define     DMA_CDSA_U2 (volatile  int ioport *)   0x0C47      //DMA Channel 2 Source Destination Address Register(upper bits)
    #define     DMA_CEN2    (volatile  int ioport *)   0x0C48      //DMA Channel 2 Element Number Register
    #define     DMA_CFN2    (volatile  int ioport *)   0x0C49      //DMA Channel 2 Frame Number Register
    #define     DMA_CSFI2   (volatile  int ioport *)   0x0C4A      //DMA Channel 2 Source Frame Index Register
    #define     DMA_CSEI2   (volatile  int ioport *)   0x0C4B      //DMA Channel 2 Source Element Index Register
    #define     DMA_CSAC2   (volatile  int ioport *)   0x0C4C      //DMA Channel 2 Source Address Counter
    #define     DMA_CDAC2   (volatile  int ioport *)   0x0C4D      //DMA Channel 2 Destination Address Counter
    #define     DMA_CDEI2   (volatile  int ioport *)   0x0C4E      //DMA Channel 2 Destination Element Index Register
    #define     DMA_CDFI2   (volatile  int ioport *)   0x0C4F      //DMA Channel 2 Destination Frame Index Register

    //**dma3**
    #define     DMA_CSDP3   (volatile  int ioport *)   0x0C60      //DMA Channel 3 Source Destination
    #define     DMA_CCR3    (volatile  int ioport *)   0x0C61      //DMA Channel 3 Control Register
    #define     DMA_CICR3   (volatile  int ioport *)   0x0C62      //DMA Channel 3 Interrupt Control Register
    #define     DMA_CSR3    (volatile  int ioport *)   0x0C63      //DMA Channel 3 Status Register
    #define     DMA_CSSA_L3 (volatile  int ioport *)   0x0C64      //DMA Channel 3 Source Start Address Register(lower bits)
    #define     DMA_CSSA_U3 (volatile  int ioport *)   0x0C65      //DMA Channel 3 Source Start Address Register(upper bits)
    #define     DMA_CDSA_L3 (volatile  int ioport *)   0x0C66      //DMA Channel 3 Source Destination Address Register(lower bits)
    #define     DMA_CDSA_U3 (volatile  int ioport *)   0x0C67      //DMA Channel 3 Source Destination Address Register(upper bits)
    #define     DMA_CEN3    (volatile  int ioport *)   0x0C68      //DMA Channel 3 Element Number Register
    #define     DMA_CFN3    (volatile  int ioport *)   0x0C69      //DMA Channel 3 Frame Number Register
    #define     DMA_CSFI3   (volatile  int ioport *)   0x0C6A      //DMA Channel 3 Source Frame Index Register
    #define     DMA_CSEI3   (volatile  int ioport *)   0x0C6B      //DMA Channel 3 Source Element Index Register
    #define     DMA_CSAC3   (volatile  int ioport *)   0x0C6C      //DMA Channel 3 Source Address Counter
    #define     DMA_CDAC3   (volatile  int ioport *)   0x0C6D      //DMA Channel 3 Destination Address Counter
    #define     DMA_CDEI3   (volatile  int ioport *)   0x0C6E      //DMA Channel 3 Destination Element Index Register
    #define     DMA_CDFI3   (volatile  int ioport *)   0x0C6F      //DMA Channel 3 Destination Frame Index Register

    //**dma4**
    #define     DMA_CSDP4   (volatile  int ioport *)   0x0C80      //DMA Channel 4 Source Destination
    #define     DMA_CCR4    (volatile  int ioport *)   0x0C81      //DMA Channel 4 Control Register
    #define     DMA_CICR4   (volatile  int ioport *)   0x0C82      //DMA Channel 4 Interrupt Control Register
    #define     DMA_CSR4    (volatile  int ioport *)   0x0C83      //DMA Channel 4 Status Register
    #define     DMA_CSSA_L4 (volatile  int ioport *)   0x0C84      //DMA Channel 4 Source Start Address Register(lower bits)
    #define     DMA_CSSA_U4 (volatile  int ioport *)   0x0C85      //DMA Channel 4 Source Start Address Register(upper bits)
    #define     DMA_CDSA_L4 (volatile  int ioport *)   0x0C86      //DMA Channel 4 Source Destination Address Register(lower bits)
    #define     DMA_CDSA_U4 (volatile  int ioport *)   0x0C87      //DMA Channel 4 Source Destination Address Register(upper bits)
    #define     DMA_CEN4    (volatile  int ioport *)   0x0C88      //DMA Channel 4 Element Number Register
    #define     DMA_CFN4    (volatile  int ioport *)   0x0C89      //DMA Channel 4 Frame Number Register
    #define     DMA_CSFI4   (volatile  int ioport *)   0x0C8A      //DMA Channel 4 Source Frame Index Register
    #define     DMA_CSEI4   (volatile  int ioport *)   0x0C8B      //DMA Channel 4 Source Element Index Register
    #define     DMA_CSAC4   (volatile  int ioport *)   0x0C8C      //DMA Channel 4 Source Address Counter
    #define     DMA_CDAC4   (volatile  int ioport *)   0x0C8D      //DMA Channel 4 Destination Address Counter
    #define     DMA_CDEI4   (volatile  int ioport *)   0x0C8E      //DMA Channel 4 Destination Element Index Register
    #define     DMA_CDFI4   (volatile  int ioport *)   0x0C8F      //DMA Channel 4 Destination Frame Index Register

    //**dma5**
    #define     DMA_CSDP5   (volatile  int ioport *)   0x0CA0      //DMA Channel 5 Source Destination
    #define     DMA_CCR5    (volatile  int ioport *)   0x0CA1      //DMA Channel 5 Control Register
    #define     DMA_CICR5   (volatile  int ioport *)   0x0CA2      //DMA Channel 5 Interrupt Control Register
    #define     DMA_CSR5    (volatile  int ioport *)   0x0CA3      //DMA Channel 5 Status Register
    #define     DMA_CSSA_L5 (volatile  int ioport *)   0x0CA4      //DMA Channel 5 Source Start Address Register(lower bits)
    #define     DMA_CSSA_U5 (volatile  int ioport *)   0x0CA5      //DMA Channel 5 Source Start Address Register(upper bits)
    #define     DMA_CDSA_L5 (volatile  int ioport *)   0x0CA6      //DMA Channel 5 Source Destination Address Register(lower bits)
    #define     DMA_CDSA_U5 (volatile  int ioport *)   0x0CA7      //DMA Channel 5 Source Destination Address Register(upper bits)
    #define     DMA_CEN5    (volatile  int ioport *)   0x0CA8      //DMA Channel 5 Element Number Register
    #define     DMA_CFN5    (volatile  int ioport *)   0x0CA9      //DMA Channel 5 Frame Number Register
    #define     DMA_CSFI5   (volatile  int ioport *)   0x0CAA      //DMA Channel 5 Source Frame Index Register
    #define     DMA_CSEI5   (volatile  int ioport *)   0x0CAB      //DMA Channel 5 Source Element Index Register
    #define     DMA_CSAC5   (volatile  int ioport *)   0x0CAC      //DMA Channel 5 Source Address Counter
    #define     DMA_CDAC5   (volatile  int ioport *)   0x0CAD      //DMA Channel 5 Destination Address Counter
    #define     DMA_CDEI5   (volatile  int ioport *)   0x0CAE      //DMA Channel 5 Destination Element Index Register
    #define     DMA_CDFI5   (volatile  int ioport *)   0x0CAF      //DMA Channel 5 Destination Frame Index Register