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PROCESSOR-SDK-J784S4: About HW mailbox interruption in IPC communication

Part Number: PROCESSOR-SDK-J784S4

In the SDK document, the IPC of C2C needs to trigger the HW mailbox interrupt. I want to ask, is it possible to trigger the interrupt storm if I communicate with high frequency for a long time?

The document also says that mailbox has a queue of 4. Does it mean that there is protection related to interruption storm?

I want to learn more about this one in detail. Thank you