在bb-black中,仿照evmAM335x中对spi0的使用(mcspiflash.c),对spi1总线进行移植,但是移植之后,发现cs0并没有拉低,而且也没有时钟信号,数据线也没有东西,请问是什么原因,时钟配置和引脚复用都做了,下面是时钟配置和引脚复用的部分代码,请大牛分析下,感觉应该没有错,但是如果这些没错的话,那么问题是出在哪里呢?谢谢了。。。
时钟配置:
void McSPI1ModuleClkConfig(void)
{
HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) =
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) =
CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) =
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) !=
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);
HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) =
CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);
HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) =
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
while((HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) !=
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) =
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL) !=
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) =
CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
CM_PER_L4LS_CLKCTRL_MODULEMODE) != CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE);
HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) &= ~CM_PER_SPI1_CLKCTRL_MODULEMODE;
HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) |=
CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE;
while((HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) &
CM_PER_SPI1_CLKCTRL_MODULEMODE) != CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE);
while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));
while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));
while(!(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK |
CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)));
while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
(CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK |
CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK)));
}
引脚复用:
int McSPIPinMuxSetup(unsigned int instanceNum)
{
unsigned int profile = 0;
int status = E_INST_NOT_SUPP;
if(0 == instanceNum)
{
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) =
(CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D0) =
(CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D1) =
(CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);
status = S_PASS;
}
else if(1 == instanceNum)
{
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI1_SCLK) =
(CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_PUTYPESEL |
CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_RXACTIVE);
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI1_D0) =
(CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_PUTYPESEL |
CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_RXACTIVE);
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI1_D1) =
(CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_PUTYPESEL |
CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_RXACTIVE);
status = S_PASS;
}
return status;
}
int McSPI1CSPinMuxSetup(unsigned int csPinNum)
{
unsigned int profile = 0;
int status = E_INVALID_CHIP_SEL;
if(MCSPI_CHANNEL_0 == csPinNum)
{
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI1_CS0) =
(CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_PUTYPESEL |
CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_RXACTIVE);
status = S_PASS;
}
return status;
}