TMS320C6678: 上电时序

外设是3.3v电平的话，是需要电平转换芯片成1.8v后，才能和DSP相连。

如果是时钟发生器，输入时钟是要在电源稳定后才能给DSP，请看数据手册上的说明。

The clock input buffers for CORECLK, DDRCLK, PASSCLK, SRIOSGMIICLK, PCIECLK and MCMCLK use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device.