在DM648上使用VP3采集来自FPGA的视频，格式是YUV422。VP口的采集模式配置成Y/C采集模式，VCTL0、VCTL1用作HSYN、VSYNC。用示波器查看VCLK0、VCTL0、VCTL1，信号正常，但是驱动程序收不到数据。用仿真器查看VCA_STAT寄存器，FSYNC, FRMC 位总是0，无EDMA中断产生，请问下这是什么原因导致的呢？VP口的配置如下：
ptPrivate->vpCapChannelParams.cmode = VPORT_MODE_YCBCR_8BIT;
ptPrivate->vpCapChannelParams.thrld = ptPrivate->uwWidth >> 3;
ptPrivate->vpCapChannelParams.fldOp = VPORT_FLDOP_PROGRESSIVE;
ptPrivate->vpCapChannelParams.scale = VPORT_SCALING_DISABLE;
ptPrivate->vpCapChannelParams.fldXStrt1 = ( ptPrivate->uwWidthMax - ptPrivate->uwWidth ) >> 1;
ptPrivate->vpCapChannelParams.fldXStop1 = ptPrivate->uwWidthMax - 1 - ptPrivate->vpCapChannelParams.fldXStrt1;
ptPrivate->vpCapChannelParams.fldXStrt2 = ( ptPrivate->uwWidthMax - ptPrivate->uwWidth ) >> 1;
ptPrivate->vpCapChannelParams.fldXStop2 = ptPrivate->uwWidthMax - 1 - ptPrivate->vpCapChannelParams.fldXStrt2;
ptPrivate->vpCapChannelParams.fldYStrt1 = 0;
ptPrivate->vpCapChannelParams.fldYStrt2 = 0;
ptPrivate->vpCapChannelParams.fldYStop1 = ptPrivate->uwHeight - 1;//(ptPrivate->uwHeight >> 1) + 2;
ptPrivate->vpCapChannelParams.fldYStop2 = ptPrivate->uwHeight - 1;//(ptPrivate->uwHeight >> 1) + 2;
ptPrivate->vpCapChannelParams.mergeFlds = VPORT_FLDS_MERGED;
ptPrivate->vpCapChannelParams.resmpl = VPORT_RESMPL_DISABLE;
ptPrivate->vpCapChannelParams.bpk10Bit = VPORTCAP_BPK_10BIT_ZERO_EXTENDED;
ptPrivate->vpCapChannelParams.hCtRst = VPORTCAP_HRST_SAV;
ptPrivate->vpCapChannelParams.vCtRst = VPORTCAP_VRST_EAV_V0;
ptPrivate->vpCapChannelParams.fldDect = VPORTCAP_FLDD_DISABLE;
ptPrivate->vpCapChannelParams.extCtl = VPORTCAP_FINV_ENABLE;
ptPrivate->vpCapChannelParams.fldInv = VPORTCAP_FLDD_DISABLE;
ptPrivate->vpCapChannelParams.numFrmBufs = 0;
ptPrivate->vpCapChannelParams.alignment = 0x80;
ptPrivate->vpCapChannelParams.segId = g_extHeap;
ptPrivate->vpCapChannelParams.autoSyncEnable = SMP_TRUE;
ptPrivate->vpCapChannelParams.hEdma = hEdma;
