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The selection for the input clock source for the SERDES, i.e., the 20 MHz reference cock or the 100 MHz differential clock, is configured via one of the SATA PLL Configuration register fields (CFGPLL0. SEL_IN_FREQ bit field located @ 0x4814_0720) where 0/1 implies external SERDES differential input/ reference 20 MHz clock input source. Note that the SATA PLL configuration registers are accessed from the device configuration register space and these registers lie within the control module space which is found in a different location from where the the SATA peripheral and PHY registers reside.
