我在定制的AM6442板卡上出现eth节点无法成功注册的情况，SDK版本：ti-processor-sdk-linux-rt-am64xx-evm-09.02.00.08，相同的板卡在ti-processor-sdk-linux-rt-am64xx-evm-08.06.00.42SDK版本中无该问题，能成功注册eth节点并进行网络通信；
报错信息如图所示，出现icssg-prueth icssg1-eth eth2: Failed to update Rx Flow ID -22的报错信息
请帮忙协助如何解决该问题；
以下是dts配置
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
compatible = "ti,am642-evm", "ti,am642";
model = "Texas Instruments AM642 EVM";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
aliases {
ethernet2 = &icssg1_emac0;
ethernet3 = &icssg1_emac1;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: m4f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
evm_12v0: fixedregulator-evm12v0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixed-regulator-sd {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
};
vddb: fixedregulator-vddb {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
mdio_mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
};
mdio_mux_1: mdio-mux-1 {
compatible = "mdio-mux-multiplexer";
mux-controls = <&mdio_mux>;
mdio-parent-bus = <&cpsw3g_mdio>;
#address-cells = <1>;
#size-cells = <0>;
mdio@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
cpsw3g_phy3: ethernet-phy@3 {
reg = <3>;
};
};
};
icssg1_eth: icssg1-eth {
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg1_rgmii1_pins_default>;
sram = <&oc_sram>;
ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
ti,mii-g-rt = <&icssg1_mii_g_rt>;
ti,mii-rt = <&icssg1_mii_rt>;
ti,pa-stats = <&icssg1_pa_stats>;
iep = <&icssg1_iep0>, <&icssg1_iep1>;
interrupt-parent = <&icssg1_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
<&main_pktdma 0xc201 15>, /* egress slice 0 */
<&main_pktdma 0xc202 15>, /* egress slice 0 */
<&main_pktdma 0xc203 15>, /* egress slice 0 */
<&main_pktdma 0xc204 15>, /* egress slice 1 */
<&main_pktdma 0xc205 15>, /* egress slice 1 */
<&main_pktdma 0xc206 15>, /* egress slice 1 */
<&main_pktdma 0xc207 15>, /* egress slice 1 */
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
<&main_pktdma 0x4201 15>, /* ingress slice 1 */
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
icssg1_emac0: port@0 {
reg = <0>;
phy-handle = <&icssg1_phy1>;
phy-mode = "rgmii-txid";
ti,syscon-rgmii-delay = <&main_conf 0x4110>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
icssg1_emac1: port@1 {
reg = <1>;
ti,syscon-rgmii-delay = <&main_conf 0x4114>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
};
};
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
};
&main_pmx0 {
pinctrl-names = "default";
pinctrl-0 = <&main_fan_pins_default &main_watchdog_pins_default &main_isolate_io_pins_default &main_4g_reset_pins_default &main_5g_pins_default>;
main_watchdog_pins_default: main_watchdog_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x011c, PIN_OUTPUT, 7) /* (AA13) PRG1_PRU1_GPO5.GPIO0_70 (watchdog WDI) */
>;
};
main_fan_pins_default: main_fan_pins_default {
pinctrl-single,pins = <
/* set the pull-up, the fan is turned on by default */
AM64X_IOPAD(0x0024, PIN_OUTPUT_PULLUP, 7) /* (N18) OSPI0_D6.GPIO0_9 (fan) */
>;
};
main_isolate_io_pins_default: main_isolate_io_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0224, PIN_OUTPUT, 7) /* (C14) SPI1_CLK.GPIO1_49 */
AM64X_IOPAD(0x0228, PIN_OUTPUT, 7) /* (B15) SPI1_D0.GPIO1_50 */
AM64X_IOPAD(0x022c, PIN_OUTPUT, 7) /* (A15) SPI1_D1.GPIO1_51 */
AM64X_IOPAD(0x021c, PIN_OUTPUT, 7) /* (B14) SPI1_CS0.GPIO1_47 */
AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* (V13) PRG1_PRU0_GPO5.GPIO0_50 */
AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* (U12) PRG1_PRU1_GPO8.GPIO0_73 */
AM64X_IOPAD(0x0268, PIN_INPUT, 7) /* (C18) I2C1_SCL.GPIO1_66 */
AM64X_IOPAD(0x026c, PIN_INPUT, 7) /* (B19) I2C1_SDA.GPIO1_67 */
>;
};
main_4g_reset_pins_default: main_4g_reset_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x029c, PIN_OUTPUT, 7) /* (C20) MMC1_SDWP.GPIO1_78 */
>;
};
main_5g_pins_default: main_5g_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0214, PIN_OUTPUT, 7) /* (A13) SPI0_D0.GPIO1_45 (5G Reset) */
AM64X_IOPAD(0x0218, PIN_OUTPUT, 7) /* (A14) SPI0_D0.GPIO1_46 (5G Power) */
>;
};
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_uart2_pins_default: main-uart2-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 3) /* (B16) UART0_CTSn.UART2_RXD */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 3) /* (A16) UART0_RTSn.UART2_TXD */
>;
};
main_uart3_pins_default: main-uart3-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 4) /* (D16) UART1_CTSn.UART3_RXD */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 4) /* (E16) UART1_RTSn.UART3_TXD */
AM64X_IOPAD(0x0174, PIN_OUTPUT, 7) /* (R3) PRG0_PRU0_GPO5.GPIO1_5 */
>;
};
main_uart6_pins_default: main-uart6-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x020c, PIN_INPUT, 5) /* (C13) SPI0_CS1.UART6_RXD */
AM64X_IOPAD(0x0220, PIN_OUTPUT, 5) /* (D14) SPI1_CS1.UART6_TXD */
AM64X_IOPAD(0x01c4, PIN_OUTPUT, 7) /* (P4) PRG0_PRU1_GPO5.GPIO1_25 */
>;
};
main_led_pins_default: main_led_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* (K17) OSPI0_CSn2.GPIO0_13 (som-led0) */
AM64X_IOPAD(0x0038, PIN_OUTPUT, 7) /* (L17) OSPI0_CSn3.GPIO0_14 (som-led1) */
AM64X_IOPAD(0x01d0, PIN_OUTPUT, 7) /* (R1) PRG0_PRU1_GPO8.GPIO1_28 (user-led0) */
AM64X_IOPAD(0x0180, PIN_OUTPUT, 7) /* (T2) PRG0_PRU0_GPO8.GPIO1_8 (user-led1) */
>;
};
main_keys_pins_default: main_keys-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 (user-key0) */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
>;
};
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
mdio1_pins_default: mdio1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
>;
};
rgmii2_pins_default: rgmii2-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
ospi0_pins_default: ospi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
>;
};
main_mcan0_pins_default: main-mcan0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
main_mcan1_pins_default: main-mcan1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
icssg0_mdio0_pins_default: icssg0-mdio0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
>;
};
icssg0_rgmii1_pins_default: icssg0-rgmii1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
AM64X_IOPAD(0x018c, PIN_INPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */
AM64X_IOPAD(0x0190, PIN_INPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */
AM64X_IOPAD(0x0194, PIN_INPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */
AM64X_IOPAD(0x0198, PIN_INPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */
AM64X_IOPAD(0x01a0, PIN_INPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
AM64X_IOPAD(0x019c, PIN_INPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */
>;
};
icssg0_rgmii2_pins_default: icssg0-rgmii2-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
AM64X_IOPAD(0x01dc, PIN_INPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */
AM64X_IOPAD(0x01e0, PIN_INPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */
AM64X_IOPAD(0x01e4, PIN_INPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */
AM64X_IOPAD(0x01e8, PIN_INPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */
AM64X_IOPAD(0x01f0, PIN_INPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
AM64X_IOPAD(0x01ec, PIN_INPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */
>;
};
icssg1_mdio1_pins_default: icssg1-mdio1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
>;
};
icssg1_rgmii1_pins_default: icssg1-rgmii1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
>;
};
icssg1_iep0_pins_default: icssg1-iep0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
>;
};
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <8>;
};
ds1340: rtc@68 {
compatible = "dallas,ds1340";
reg = <0x68>;
trickle-resistor-ohms = <250>;
};
isl1280:rtc@6f{
compatible = "isil,isl1208";
reg = <0x6f>;
uie-disabled;
};
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
&main_uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart2_pins_default>;
};
&main_uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart3_pins_default>;
rts-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
};
&main_uart4 {
status = "disabled";
};
&main_uart5 {
status = "disabled";
};
&main_uart6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart6_pins_default>;
rts-gpios = <&main_gpio1 25 GPIO_ACTIVE_LOW>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
};
&mcu_uart0 {
status = "disabled";
};
&mcu_uart1 {
status = "disabled";
};
&main_i2c1 {
status = "disabled";
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_i2c0 {
status = "disabled";
};
&mcu_i2c1 {
status = "disabled";
};
&mcu_spi0 {
status = "disabled";
};
&mcu_spi1 {
status = "disabled";
};
&sdhci0 {
/* emmc */
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&usbss0 {
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "host";
maximum-speed = "high-speed";
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
&rgmii2_pins_default>;
cpts@3d000 {
ti,pps = <7 1>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
phy-address-broadcast-off;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
phy-address-broadcast-off;
};
};
#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val)
×ync_router {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpts_pps>;
/* Example of the timesync routing */
mcu_cpts_pps: mcu-cpts-pps {
pinctrl-single,pins = <
/* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */
TS_OFFSET(37, 22)
/* pps [cpts genf1] in22 -> out25 [SYNC1_OUT pin] */
TS_OFFSET(25, 22)
>;
};
};
&mailbox0_cluster2 {
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&pcie0_rc {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&pcie0_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};
&tscadc0 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
cdns,phy-mode;
#address-cells = <1>;
#size-cells = <1>;
};
};
&main_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
};
&main_mcan1 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
};
&icssg0_mdio {
pinctrl-names = "default";
pinctrl-0 = <&icssg0_mdio0_pins_default>;
icssg0_phy1: ethernet-phy@2 {
reg = <2>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
icssg0_phy2: ethernet-phy@3 {
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&icssg1_mdio {
pinctrl-names = "default";
pinctrl-0 = <&icssg1_mdio1_pins_default>;
icssg1_phy1: ethernet-phy@4 {
reg = <4>;
tx-internal-delay-ps = <250>;
rx-internal-delay-ps = <2000>;
};
};
&icssg1_iep0 {
pinctrl-names = "default";
pinctrl-0 = <&icssg1_iep0_pins_default>;
};
