想用VPORT1进行视频采集，VPORT0用作MCBSP做串口传输，串口是用EDMA中断做的，发现只要用FVID_create配置过VPORT1后，就进不去串口的中断函数了，不配置VPORT1的话，串口工作正常。不知道该从哪下手，请高手指点一二。
VPORT1配置函数为capChan = FVID_create("/VP1CAPTURE/A/1", IOM_INPUT, &status, (Ptr)&EVMDM642_vCapParamsChan, NULL);
VPORTCAP_Params EVMDM642_vCapParamsChan = {
VPORT_CMODE, /* cmode:3 */
VPORT_FLDOP_PROGRESSIVE, /* fldOp:3 */
VPORT_SCALING_DISABLE, /* scale:1 */ // n/a for raw
VPORT_RESMPL_DISABLE, /* resmpl:1 */ // n/a for raw
VPORTCAP_BPK_10BIT_ZERO_EXTENDED, /*bpk10Bit:2 */
VPORTCAP_HRST_SAV, /*hCtRst:1 */ // n/a for raw
VPORTCAP_VRST_EAV_V0, /*vCtRst:1 */ // n/a for raw
VPORTCAP_FLDD_DISABLE, /*fldDect:1 */ // n/a for raw
VPORTCAP_EXC_DISABLE, /*extCtl:1 */ // n/a for raw
VPORTCAP_FINV_ENABLE, /* fldInv:1 */ // n/a for raw
/* Raw Mode Specific Parameters */
VPORTCAP_SSE_ENABLE, /*sse*/ // Enable Startup Sync
0x7FF, /*vcvblnkp*/
0, /*fldXStrt1 */ // Must set to zero for correct operation
1, /*fldYStrt1 */ // Must set to one for correct operation
0, /*fldXStrt2 */ // Must equal fldXStrt1 for correct operation
1, /*fldYStrt2 */ // Must equal fldYStrt2 for correct operation
NULL, // fill later /*fldXStop1 */ // must subtract 1 for correct operation
NULL, // fill later /*fldYStop1 */ // These two parameters are used to set Field 1 stop register
NULL, // fill later /*fldXStop2 */ // Must equal fldXStop1 for correct operation
NULL, // fill later /*fldYStop2 */ // Must equal fldYStop1 for correct operation
NULL, // fill later
3, /*numFrmBufs*/
128, /*alignment */
VPORT_FLDS_MERGED, /*mergeFlds */
NULL, /*segId */
EDMA_OPT_PRI_HIGH, /*edmaPri */
8 /* irqId */
};
串口配置为void ConfigMcBSP(void)
{
MCBSP_Config mcbspCfg1 = {
/* SPCR Setup */
#if (DMA_SUPPORT)
MCBSP_SPCR_RMK(
MCBSP_SPCR_FRST_DEFAULT, /* 0 */
MCBSP_SPCR_GRST_DEFAULT, /* 0 */
MCBSP_SPCR_XINTM_XRDY, /* 00 */
MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
MCBSP_SPCR_XRST_DEFAULT, /* 0 */
MCBSP_SPCR_DLB_OFF, /* 0 */
MCBSP_SPCR_RJUST_RZF, /* 00 */
MCBSP_SPCR_CLKSTP_DISABLE, /* 0x */
MCBSP_SPCR_RINTM_RRDY, /* 00 */
MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
MCBSP_SPCR_RRST_DEFAULT /* 0 */
),
#endif
#if (EDMA_SUPPORT)
MCBSP_SPCR_RMK(
MCBSP_SPCR_FREE_YES, /* 1 */
MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
MCBSP_SPCR_FRST_DEFAULT, /* 0 */
MCBSP_SPCR_GRST_DEFAULT, /* 0 */
MCBSP_SPCR_XINTM_XRDY, /* 00 */
MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
MCBSP_SPCR_XRST_DEFAULT, /* 0 */
MCBSP_SPCR_DLB_OFF, /* 0 */
MCBSP_SPCR_RJUST_RZF, /* 00 */
MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
MCBSP_SPCR_DXENA_OFF, /* 0 */
MCBSP_SPCR_RINTM_RRDY, /* 00 */
MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
MCBSP_SPCR_RRST_DEFAULT /* 0 */
),
#endif
/* RCR Setup */
#if (DMA_SUPPORT)
MCBSP_RCR_RMK(
MCBSP_RCR_RPHASE_DUAL, /* 1 */
MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
MCBSP_RCR_RCOMPAND_MSB, /* 00 */
MCBSP_RCR_RFIG_YES, /* 1 */
MCBSP_RCR_RDATDLY_1BIT, /* 01 */
MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
MCBSP_RCR_RWDLEN1_16BIT /* 010 */
),
#endif
#if (EDMA_SUPPORT)
MCBSP_RCR_RMK(
MCBSP_RCR_RPHASE_DUAL, /* 1 */
MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
MCBSP_RCR_RCOMPAND_MSB, /* 00 */
MCBSP_RCR_RFIG_YES, /* 1 */
MCBSP_RCR_RDATDLY_1BIT, /* 01 */
MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
),
#endif
/* XCR Setup */
#if (DMA_SUPPORT)
MCBSP_XCR_RMK(
MCBSP_XCR_XPHASE_DUAL, /* 1 */
MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
MCBSP_XCR_XWDLEN2_8BIT, /* 000 */
MCBSP_XCR_XCOMPAND_MSB, /* 00 */
MCBSP_XCR_XFIG_YES, /* 1 */
MCBSP_XCR_XDATDLY_0BIT, /* 00 */
MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
MCBSP_XCR_XWDLEN1_16BIT /* 010 */
),
#endif
#if (EDMA_SUPPORT)
MCBSP_XCR_RMK(MCBSP_XCR_XPHASE_DUAL,
MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
MCBSP_XCR_XWDLEN2_16BIT, /* 000 */
MCBSP_XCR_XCOMPAND_MSB, /* 00 */
MCBSP_XCR_XFIG_YES, /* 1 */
MCBSP_XCR_XDATDLY_0BIT, /* 00 */
MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
),
#endif
/* SRGR Setup */
MCBSP_SRGR_RMK(
MCBSP_SRGR_GSYNC_FREE, /* 0 */
MCBSP_SRGR_CLKSP_RISING, /* 0 */
MCBSP_SRGR_CLKSM_INTERNAL, /* 1 */
MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
MCBSP_SRGR_FPER_DEFAULT, /* 0 */
MCBSP_SRGR_FWID_DEFAULT, /* 0 */
MCBSP_SRGR_CLKGDV_OF(81) /* CLKGDV */
),
/* MCR Setup */
MCBSP_MCR_DEFAULT, /* default values */
/* RCER Setup */
#if (C64_SUPPORT)
MCBSP_RCERE0_DEFAULT, /* default values */
MCBSP_RCERE1_DEFAULT, /* default values */
MCBSP_RCERE2_DEFAULT, /* default values */
MCBSP_RCERE3_DEFAULT, /* default values */
#else
MCBSP_RCER_DEFAULT, /* default values */
#endif
/* XCER Setup */
#if (C64_SUPPORT)
MCBSP_XCERE0_DEFAULT, /* default values */
MCBSP_XCERE1_DEFAULT, /* default values */
MCBSP_XCERE2_DEFAULT, /* default values */
MCBSP_XCERE3_DEFAULT, /* default values */
#else
MCBSP_XCER_DEFAULT, /* default values */
#endif
/* PCR Setup */
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_SP, /* 0 */
MCBSP_PCR_RIOEN_SP, /* 0 */
MCBSP_PCR_FSXM_INTERNAL, /* 1 */
MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
MCBSP_PCR_CLKSSTAT_0, /* 0 */
MCBSP_PCR_DXSTAT_0, /* 0 */
MCBSP_PCR_FSXP_ACTIVELOW, /* 1 */
MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
MCBSP_PCR_CLKXP_RISING, /* 0 */
MCBSP_PCR_CLKRP_FALLING /* 0 */
)
};
MCBSP_config(hMcbsp0, &mcbspCfg1);
}
串口EDMA配置为void ConfigEDMA(unsigned char u8Ch, unsigned char u8Count)
{
switch(u8Ch)
{
case 12:
EDMA_configArgs(hEdma12,
/* OPT Setup */
#if (C64_SUPPORT)
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* 1 */
EDMA_OPT_ESIZE_16BIT, /* 01 */
EDMA_OPT_2DS_NO, /* 0 */
EDMA_OPT_SUM_INC, /* 01 */
EDMA_OPT_2DD_NO, /* 0 */
EDMA_OPT_DUM_NONE, /* 00 */
EDMA_OPT_TCINT_YES, /* 1 */
EDMA_OPT_TCC_OF(12), /* 14 */
EDMA_OPT_TCCM_DEFAULT, /* 0 */
EDMA_OPT_ATCINT_DEFAULT, /* 0 */
EDMA_OPT_ATCC_DEFAULT, /* 0 */
EDMA_OPT_PDTS_DEFAULT, /* 0 */
EDMA_OPT_PDTD_DEFAULT, /* 0 */
EDMA_OPT_LINK_NO, /* 0 */
EDMA_OPT_FS_NO /* 0 */
),
#else
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* 1 */
EDMA_OPT_ESIZE_16BIT, /* 01 */
EDMA_OPT_2DS_NO, /* 0 */
EDMA_OPT_SUM_INC, /* 01 */
EDMA_OPT_2DD_NO, /* 0 */
EDMA_OPT_DUM_NONE, /* 00 */
EDMA_OPT_TCINT_YES, /* 1 */
EDMA_OPT_TCC_OF(12), /* 14 */
EDMA_OPT_LINK_NO, /* 0 */
EDMA_OPT_FS_NO /* 0 */
),
#endif
/* SRC Setup */
EDMA_SRC_RMK((Uint32) xmitbuf), /*xmitbuf address*/
/* CNT Setup */
EDMA_CNT_RMK(
EDMA_CNT_FRMCNT_DEFAULT,
EDMA_CNT_ELECNT_OF(u8Count*11) //Mcbsp Xm phase2 is 8bit
),
/* DST Setup */
EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp0)),
/* IDX Setup */
EDMA_IDX_RMK(0,0),
/* RLD Setup */
EDMA_RLD_RMK(0,0)
);
break;
case 13:
EDMA_configArgs(hEdma13,
/* OPT Setup */
#if (C64_SUPPORT)
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* 1 */
EDMA_OPT_ESIZE_16BIT, /* 01 */
EDMA_OPT_2DS_NO, /* 0 */
EDMA_OPT_SUM_NONE, /* 00 */
EDMA_OPT_2DD_NO, /* 0 */
EDMA_OPT_DUM_INC, /* 01 */
EDMA_OPT_TCINT_YES, /* 1 */
EDMA_OPT_TCC_OF(13), /* 15 */
EDMA_OPT_TCCM_DEFAULT, /* 0 */
EDMA_OPT_ATCINT_DEFAULT, /* 0 */
EDMA_OPT_ATCC_DEFAULT, /* 0 */
EDMA_OPT_PDTS_DEFAULT, /* 0 */
EDMA_OPT_PDTD_DEFAULT, /* 0 */
EDMA_OPT_LINK_NO, /* 0 */
EDMA_OPT_FS_NO /* 0 */
),
#else
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* 1 */
EDMA_OPT_ESIZE_16BIT, /* 01 */
EDMA_OPT_2DS_NO, /* 0 */
EDMA_OPT_SUM_NONE, /* 00 */
EDMA_OPT_2DD_NO, /* 0 */
EDMA_OPT_DUM_INC, /* 01 */
EDMA_OPT_TCINT_YES, /* 1 */
EDMA_OPT_TCC_OF(13), /* 15 */
EDMA_OPT_LINK_NO, /* 0 */
EDMA_OPT_FS_NO /* 0 */
),
#endif
/* SRC Setup */
EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp0)),
/* CNT Setup */
EDMA_CNT_RMK(0, (RFRAME_BUFFER_SIZE * 11)),//(RFRAME_BUFFER_SIZE * 11)),
/* DST Setup */
EDMA_DST_RMK((Uint32) recvbuf), /*recvbuf address*/
/* IDX Setup */
EDMA_IDX_RMK(0,0),
/* RLD Setup */
EDMA_RLD_RMK(0,0)
);
break;
default:
break;
} //end of switch
}
串口中断函数为
Void c_int08(Void)
{
//HWI_enter();
#if (EDMA_SUPPORT)
if (EDMA_intTest(12))
{
EDMA_intClear(12);
//transmit_done = TRUE;
//post SEM1
SWI_post(&SWI1); //post mcbsp Xm swi
//LOG_printf(&trace, "Transmit Completed\n");
}
if (EDMA_intTest(13))
{
EDMA_intClear(13);
//receive_done = TRUE;
//ConfigEDMA(13,0); //rev channel
SWI_post(&SWI0); //post mcbsp rev swi
//LOG_printf(&trace, "Receive Completed\n\n");
}
#endif
//HWI_exit();
}