C6678 多核启动，内存不稳定，数据跳动

   int i;

    if (CSL_chipReadReg(CSL_CHIP_DNUM) == 0)     {      CACHE_setL1PSize(CACHE_L1_32KCACHE);      CACHE_setL1DSize(CACHE_L1_0KCACHE);      CACHE_setL2Size(CACHE_0KCACHE);      //CACHE_invAllL1p(CACHE_WAIT);      //CACHE_wbInvAllL1d(CACHE_WAIT);      //CACHE_wbInvAllL2(CACHE_WAIT);     }     else     {      CACHE_setL1PSize(CACHE_L1_32KCACHE);      CACHE_setL1DSize(CACHE_L1_32KCACHE);      CACHE_setL2Size(CACHE_0KCACHE);      //CACHE_invAllL1p(CACHE_WAIT);      //CACHE_wbInvAllL1d(CACHE_WAIT);      //CACHE_wbInvAllL2(CACHE_WAIT);     }

 /*make other cores local memory cacheable and prefetchable*/  for(i=16; i<24; i++)   CGEM_regs->MAR[i]=1|(1<<CSL_CGEM_MAR0_PFX_SHIFT);

 /*make DDR cacheable and prefetchable*/  for(i=128; i<256; i++)  {   if ( i != 131)   {    CGEM_regs->MAR[i]=1|(1<<CSL_CGEM_MAR0_PFX_SHIFT);   }   else   {    CGEM_regs->MAR[i]=0;   }  }  /*make other space non-cacheable and non-prefetchable*/  for(i=24; i<128; i++)   CGEM_regs->MAR[i]=0;

 /*XMC memory address extension/mapping and memory protection*/  KeyStone_XM_cfg();

 //DSP core speed  //KeyStone_main_PLL_init (20, 1);  //for 50MHz input clock  KeyStone_main_PLL_init (12,1);  //for 100MHz input clock  //DDR speed = 66.67*20/1= 1333  KeyStone_DDR_PLL_init (20, 1);  Shannon_EVM_DDR_Init(666.667);  //for 1333Mbps  serdes_cfg.commonSetup.inputRefClock_MHz = 156.25;     TSC_init(); //initialize TSC to measure cycle

多核启动下，在上面代码后加入DDR3写操作，会出现DDR数据跳变，不稳定；加入一定延时再赋值，就比较稳定，求解答为什么这样？