你好，我用的是C6745的DSP，SPI1接口通过EDMA3与外部的ARM进行通信，在EDMA3配置中准备发送300个16位的数据，但只发送了第一个数据，请问是什么原因呢？
SPI1接口和EMDA3初始化代码如下：
void C6745_SPI1_Init(void)
{
/* Reset SPI */
SPI1_GCR0 = 0;
C6745_wait( 1000 );
/* Release SPI */
SPI1_GCR0 = 1;
/* SPI 4-Pin Mode setup */
SPI1_GCR1 = 0
| ( 0 << 24 ) // ENABLE
| ( 0 << 16 ) // LOOPBACK
| ( 1 << 1 ) // CLKMOD
| ( 1 << 0 ); // MASTER/SLAVE Setup Slave MODE
// SPI_SPIPC0 = 0
SPI1_PC0 = 0
| ( 1 << 11 ) // SOMIFUN
| ( 1 << 10 ) // SIMOFUN
| ( 1 << 9 ) // CLKFUN
| ( 0 << 8 ) // ENAFUN
| ( 0 << 1 ) // EN1
| ( 1 << 0 ); // SCS[0]
SPI1_PC1 = 0
| ( 0 << 11 ) // SOMIFUN
| ( 1 << 10 ) // SIMOFUN
| ( 1 << 9 ) // CLKFUN
| ( 1 << 8 ) // ENAFUN
| ( 1 << 0 ); // SCS[0]
// SPI_SPIFMT0 = 0
SPI1_FMT0 = 0
| ( 0 << 24 ) // WDELAY(bit29-24) :value :0-3Fh sprufm4i
| ( 0 << 20 ) // SHIFTDIR
| ( 1 << 18 )
| ( 0 << 17 ) // Polarity: SPI clock polarity
| ( 0 << 16 ) // Phase: SPI clock delay
| ( 149 << 8 ) // Prescale to 1MHz 150MHz/(149+1)=1MHz
| ( 16 << 0 ); // Char Len: SPI data word length value:2-10h
// spidat1 = 0
spi1dat1 = 0
| ( 1 << 28 ) // CSHOLD: Chip select hold mode
| ( 0 << 24 ) // Format [0]: Data word format select
| ( 0 << 25 )
| ( 0 << 16 ) // CSNR [only CS0 enbled] Chip select number,When the SPI is comfigured in slave mode,this field
// must be written as 00h
| ( 0 << 0 ); //
SPI1_DAT1 = spi1dat1;
// SPI_SPIDELAY = 0
SPI1_DELAY = 0 // SPIDELAY is used in master only
| ( 8 << 24 ) // C2TDELAY
| ( 8 << 16 ); // T2CDELAY
// SPI_SPIDEF = 0
SPI1_DEF = 0 // SPI Default Chip Select Register, in slave mode,the CSDEF field should be set to FFh.
| ( 0 << 1 ) // EN1 inactive high
| ( 1 << 0 ); // EN0 inactive high
// SPI1_DEF = 0xFF; // SPI Default Chip Select Register, in slave mode,the CSDEF field should be set to FFh.
// SPI_SPIINT = 0
SPI1_INT0 = 0 // SPI Interrupt Register
| ( 0 << 16 ) // DMA request enable
| ( 0 << 9 ) // TXINTENA
| ( 0 << 8 ) // RXINTENA
| ( 0 << 6 ) // OVRNINTENA
| ( 0 << 4 ); //
SPI1_SPILVL = 0
| ( 1 << 9 ) // Transmit interrupt level
| ( 1 << 8 ) // Receive interrupt level
| ( 0 << 6 ) // EN0
| ( 0 << 4 ); // EN0
/* Enable SPI */
SPI1_SPIGCR1 |= ( 1 << 24 );
/*Enable DMA request*/
SPI1_INT0 = 0 // SPI Interrupt Register
| ( 1 << 16 ) // DMA request enable
| ( 0 << 9 ) // TXINTENA
| ( 0 << 8 ) // RXINTENA
| ( 0 << 6 ) // OVRNINTENA
| ( 0 << 4 ); //
}
void SPI1_DMAConfig( void )
{
// Clear Event Missed Clear Registers
EMCR = 0
| ( 1 << 19 );
// Clear Event Registers
ECR = 0x000C0000; //clear the SPI1 Transmit (19) and Recieve(18) event
SECR = 0x000C0000; //clear the SPI1 Transmit (19) and Recieve(18) Secondary event
//Clear EDMA3 Interrupt pending register(IPR)
EDMA3_ICR |= 0x000C0000; //clear the flag
// Initialize PaRAM Transfer Context for Event 19
SPI1TRA_OPT = 0
| ( 0 << 2 ) //A-synchronized
| ( 0 << 3 ) //not static
| ( 0 << 1 ) // DAM: Increment mode /don't use the fifo
| ( 0 << 0 ) // DAM: Increment mode /don't use the fifo
| ( 19 << 12 ) //set tcc 19
| ( 0 << 21 ) // Intermediate transfer completion interrupt is disnabled
| ( 1 << 20 ) //inturup enabled,the last tr trigger interupt
| ( 1 << 8 ) //16 BIT FIFO(not be used)
| ( 0 << 11 ); //Transfer complete code mode. Normal completion /EACH TR ONE INTERUPT
SPI1TRA_SRC = (Uint32)TraData;
SPI1TRA_A_B_CNT = 0x012C0002;//300 group,16 bit
SPI1TRA_DST = 0x01E12038;//SPI1_SPIDAT1;
SPI1TRA_LINK_BCNTRLD = 0x0000FFFF; //0x00084F80;
SPI1TRA_CCNT = 0x00000001;//one frame,SEND ONCE
SPI1TRA_SRC_DST_BIDX = 0x00000002;
DMAQNUM2 = 0x00001000; // Assign Channel 18 to Queue 1,Assign Channel 19 to Queue 0
DRAE1 = 0x00080000; // Enable Channel 18 and 19 to DSP (Region 1)
EESR = 0x00080000; //Enable EDMA3 Event18 and Event19 // Enable Channel 18 and 19 Event Register
IESR = 0x00080000; //Enable EDMA3 Event18 and Event19 Interrupt
}
CMD文件如下：
/*
* Copyright 2008 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/
/*
* Linker command file
*
*/
-l C6747bsl.lib
-stack 0x00001000 /* Stack Size */
-heap 0x00001000 /* Heap Size */
MEMORY
{
VECS: o = 0x11800000 l = 0x00000f00
ARMRAM: o = 0xFFFF0080 l = 0x00001f80
DSPL2ROM: o = 0x00700000 l = 0x000FFFFF
DSPL2RAM: o = 0x00800F00 l = 0x0003F100
DSPL2RAM2: o = 0x11800f00 l = 0x0003F100
SDRAM: o = 0xC0000000 l = 0x07ffffff
}
SECTIONS
{ ".vectors" > VECS
.bss > DSPL2RAM2
.cinit > DSPL2RAM2
.cio > DSPL2RAM2
.const > DSPL2RAM2
.stack > DSPL2RAM2
.sysmem > DSPL2RAM2
.text > DSPL2RAM2
.switch > DSPL2RAM2
.far > DSPL2RAM2
.calcbuffer > DSPL2RAM2
.compxbuf > DSPL2RAM2
.bufs > DSPL2RAM2
.buffer > SDRAM
.buffertemp > SDRAM
.compxbuffer> SDRAM
adc1_ram > SDRAM
adc2_ram > SDRAM
adc3_ram > SDRAM
adc4_ram > SDRAM
}