K7芯片和66AK2H14的DSPcore0通过x1链路连接，链路速率为设置为2.5Gbps。DSP端为noloopback模式，dspnum设置为1。FPGA端采用xilinx的SRIO gen2 1.6 ，通过NWRITE向DSP的core0 L2空间发送数据，但DSP端没有检测到数据输入。DSP端报文给出的链路状态如下：
Input port 0 next expected ackID value: 0x2
Output port 0 unacknowledged ackID: 0x0
Output port 0 next transmitted ackID value: 0x0
The output port 0 has encountered a failed condition. The failed port error threshold has been reached in the Port n Error Rate Threshold Register.
The output port 0 has encountered a degraded condition. The degraded port error threshold has been reached in the Port n Error Rate Threshold Register.
The output port 0 has encountered (and possibly recovered from) a transmission error. This bit is set when bit 16 is set.
The input port 0 has encountered (and possibly recovered from) a transmission error. This bit is set when bit 8 is set.
The input port 0 is in the input error-stopped state.
Port 0 OK condition. The input and output ports are initialized, and the port is exchanging error-free control symbols with the attached device.
The port 0 received a packet-not-accepted acknowledge control symbol.
The port 0 detected a delineation error. The port received an unaligned /SC/ or /PD/ or undefined code-group. The capture registers do not have valid information during this error detection.
The port 0 experienced a link timeout. The port did not receive an acknowledge or link-response control symbol within the specified time-out interval. The capture registers do not have valid information during this error detection.
Type of information logged: 2 (0 - packet, 1 - control symbol)
captured error bit in the Port Error Detect Register: 11
control symbol or Bytes 0 to 3 of the packet header that correspond to the error: 0x1c40ff00
Bytes 4 to 7 of the packet header that corresponds to the error: 0x0
Bytes 8 to 11 of the packet header that corresponds to the error: 0x0
Bytes 12 to 15 of the packet header that corresponds to the error: 0x0
15 8b/10b deconding error have occurred
SP[0]_ERR_STAT = 0x03020102
SP[0]_ERR_DET = 0x00100005
Corrected Error Stop Condition. SP[0]_ERR_STAT = 0x03020101
Clearing Errors.
FPGA端chipscope能够检查到port_initialized和link_initialized信号为高，但多采集几次偶尔能发现它们被拉低之后再置高。这是否表明物理层链路上存在问题？检查过板卡布局布线，还没发现有什么大的错误。请各位高手们不吝赐教！
