有关6748无操作系统的UPP请教

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6748只用来接收FPGA发送的数据，按照TI给出的6748的TRM中的第1479页描述的步骤配置为UPP部分之后，UPP中断函数也是按照TRM给出的参考代码来编写。

1. Apply the appropriate pin multiplexing settings. See the System Configuration (SYSCFG) Module
chapter, your device-specific data manual, and/or pin multiplexing utility for more information.
2. Enable the power and clocks to the uPP peripheral. See the Device Clocking chapter for more
information.
3. Set the SWRST bit in the uPP peripheral control register (UPPCR) to 1 to place uPP in software reset.
4. Wait at least 200 device clock cycles, then clear the SWRST bit to 0 to bring the module out of reset.
5. Program the uPP configuration registers: UPCTL, UPICR, UPIVR, UPTCR, and UPDLB. The basic
function of each register is summarized here; for more information, see Section 31.3.
(a) UPCTL – Transmit/receive selection (see Table 31-7), data width, data format, data rate, data
interleave enable
(b) UPICR – Signal enable, signal inversion, clock divisor (transmit only)
(c) UPIVR – Idle value (transmit only)
(d) UPTCR – I/O transmit threshold (transmit only), DMA read burst size
(e) UPDLB – Digital loopback (see Table 31-7)
6. Program the uPP interrupt enable set register (UPIES) to interrupt generation for the desired events.
Register an interrupt service routine (ISR) if desired; otherwise, polling is required.
7. Set the EN bit in the uPP peripheral control register (UPPCR) to 1 to turn on the uPP peripheral.
8. Allocate and/or initialize data buffers for use with uPP.
9. Program the DMA channels with their first transfers using the uPP DMA channel descriptor registers:
UPID0-2 and/or UPQD0-2.
10. Watch for interrupt events. Reprogram the DMA as necessary (checking that the PEND bit in the uPP
DMA channel status register (UPxS2) is 0).
(a) If polling, check UPIES. Reading a bit as 1 indicates the corresponding event has occurred. Write
the corresponding bit with 1 to clear.
(b) If using ISR, check UPIES inside your ISR. Structure your ISR according to the pseudo-code in