6748中upp的UPICR中CLKINVA位的请教

Victorsunhao

Expert 1444 points

6748中upp的UPICR中CLKINVA位，TI的手册上的描述是：

Channel A clock inversion. Controls clock signal polarity for interface Channel A.

0 Clock is not inverted. Channel A signals align on rising edge of clock.

1 Clock is inverted. Channel A signals align on falling edge of clock.

请问当CLKINVA 位为0 的时候， signal align on rising edge of clock. 指的是数据在传输是发生在时钟的上升沿？还是指的是这些upp有关的信号线是在上升沿的时候开始对齐？？？

请指导，谢谢！！

10 年多前

0 Tony Tang 9 年多前

TI__Guru 64206 points

TRM手册：

33.2.5.6 CLOCK Signal
The uPP transmitter drives the CLOCK signal to align all other uPP signals. By default, other signals align
on the rising edge of CLOCK, but its polarity is controlled by the CLKINVx bit in UPICR. The active
edge(s) of CLOCK should always slightly precede transitions of other uPP signals.
In transmit mode, CLOCK is an output signal; in receive mode, CLOCK is an input signal. See
Section 33.2.1 for more information on clock generation and allowed frequencies.

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6748中upp的UPICR中CLKINVA位的请教