DSP给FPGA发送一个数据后，CE2n信号一直为低，TED、TEA一直为刚发的数据地址和数据。
/* EMIF配置 */
*(int *)EMIF_GCTL = 0x00003060;/* EMIF global control register */
*(int *)EMIF_CE1 = 0xFFFFFF23; /* CE1 - 16-bit asynch access */
*(int *)EMIF_CE0 = 0xFFFFFF30; /* CE0 - SDRAM */
*(int *)EMIF_CE2 = 0x3233C823; /* CE2 - 32-bit asynch on daughterboard */
*(int *)EMIF_CE3 = 0xFFFFFF13; /* CE3 - 32-bit asynch on daughterboard */
