先描述一下问题，我的MCBSP是和FPGA交互数据，DSP发送数据，FPGA接收数据，每个字16bit，每帧20个字，帧同步和时钟均由FPGA提供。现在遇到的问题是DSP第一次发送串口数据时，FPGA端接收到的第一个字为0，第二个字才是DSP端想要发的第一个数据，且DSP要发的最后一个数据没有发出去。以后每帧发送数据的第一个字均为前一个帧的最后一个字。此问题已困扰我好几天了。由于帧同步与时钟都是FPGA提供，所以我发送口的时钟发生器没有配置并且没有使能。我的程序代码以及MCBSP发送口的配置如下：
void vSendMcbspFrame(ST_MCBSP_FRAME *ptMcbspFrame)
{
UINT16 i = 0;
asm(" BSET INTM ");
memcpy(auMcbspXmt, (UINT16 *)&(ptMcbspFrame->muFrameHead), sizeof(ST_MCBSP_FRAME));
while(i < 20) //MCBSP_FRAME_LEN
{
while(0x0002 != (SPCR20 & 0x0002)));
DXR10 = auMcbspXmt[i];
i++;
}
asm(" BCLR INTM ");
}
/* configer the transimit */
//step1 : reset the transmint
SPCR20 &= 0xFF3E; //FRST = 0 GRST = 0 XRST = 0
//step2 : setting the pin as MCBSP
PCR0 &= 0xDFFF; //XIOEN = 0
//step3 : disable the digital loop back mode
SPCR10 &= 0x7FFF; // DLB = 0
//step4 : disable the clock stop mode
SPCR10 &= 0xEFFF; //CLKSTP = 0x
//step5 : disable the transmit multichannel selection
MCR20 &= 0xFFFC; //XMCM = 00
//step6 : select the sigle phase frame
XCR20 &= 0x7FFF; //XPHASE = 0
//step7 : setting the transmit word length as 16bit
XCR10 &= 0xFF1F;
XCR10 |= 0x0040; //XWDLEN1 = 010
//step8 : setting the transmit frame length as 26
XCR10 &= 0x80FF;
XCR10 |= 0x1300; // XFRLEN1 = 19 19 + 1 = 20 words per frame
//step9 : enable the transmit frame sync ignor fuction
// XCR20 |= 0x0004; // XFIG = 1
//step10: setting the transimit compand mode
XCR20 &= 0xFFE7; //XCOMPAND = 00
//step11: setting the transmint data delay as 0 delay
XCR20 &= 0xFFFC; //XDATDLY = 00
//step12: setting the transmit DXENA mode as off
SPCR10 &= 0xFF7F; //DXENA = 0
//step13: setting the transmit interrupt mode
SPCR20 |= 0x0020; //XINTM = 10
//step14: setting the transmit frame sync mode
PCR0 &= 0xF7FF; //FSXM = 0
//step15: setting the transmit frame sync polarity
PCR0 &= 0xFFF7; //FSXP = 0
//step16: setting the SRG frame sync period and pulse width
// do nothing
//step17: setting the transmit clock mode as external clock via the CLKX pin
PCR0 &= 0xFDFF; // CLKXM = 0
//step18 setting the transmit clock polarity
PCR0 &= 0xFFFD;
//step19 setting the SRG clock divide down value
//do nothing
//step20 setting the SRG clock synchronization mode
SRGR20 |= 0x8000;
//do nothing
//step21 setting the SRG clock mode
PCR0 &= 0xFF7F; //for acture
SRGR20 &= 0xDFFF; //for acture
//step22 setting the SRG input clock polarity
//do nothing
// last step enable the transimit
SPCR20 |= 0x0001;
