6678 DDR初始化相关问题

Zhang Jerry

在DDR初始化遇到一些问题：

1、在软仿真时观测到DDR_Regs在Memory Browser里的内存分配和赋值都是正确的，但硬仿真时Memory Browser里观测到DDR_Regs->RDWR_LVL_CTRL所给赋值却是一个错误的值，这是为什么呢？

2、遇到同样的问题boot_cfg_regs软仿真时在Memory Browser里的内存分配和赋值都是正确的，但硬仿真时发现boot_cfg_regs->KICK_REG0 = 0x83e70b13;
boot_cfg_regs->KICK_REG1 = 0x95a4f1e0;等不能赋值，boot_cfg_regs->DDR3_CONFIG_REG[0] |= 0xF; boot_cfg_regs->DDR3_CONFIG_REG[23]|=0x00000200;赋值错误。

请大家帮忙分析一下！

谢谢！

13 年多前

0 Bruce Chen1 13 年多前

Expert 1775 points

您好！

方便的话上传你的代码，供大家分析。

0 Zhang Jerry 13 年多前回复 Bruce Chen1

Prodigy 140 points

你好！

附件里的程序是根据我们的需要对例程里相对应程序改编的，遇到的问题如上，请大家帮忙分析！

谢谢！

全屏 KeyStone_DDR_Init.c 下载

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 /****************************************************************
 * KeyStone_DDR_Init.c
 *
 * Created on: 2012-5-4
 *
 * Author: ZhangXiang
 *****************************************************************/
#include <stdio.h>
#include <csl_bootcfgAux.h>
#include "KeyStone_DDR_Init.h"
CSL_Emif4fRegs * DDR_Regs = (CSL_Emif4fRegs*) CSL_DDR3_EMIF_CONFIG_REGS;//0x21000000
CSL_BootcfgRegs * boot_cfg_regs = (CSL_BootcfgRegs*) CSL_BOOT_CFG_REGS;//0x02620000
void Shannon_EVM_DDR_Init(float clock_MHz)
{
    //CSL_Emif4fRegs * DDR_Regs = (CSL_Emif4fRegs*) CSL_DDR3_EMIF_CONFIG_REGS;
    //CSL_BootcfgRegs * boot_cfg_regs = (CSL_BootcfgRegs*) CSL_BOOT_CFG_REGS;
    printf("configure DDR at %d MHz\n", (unsigned int)clock_MHz);
    CSL_BootCfgUnlockKicker();
    //boot_cfg_regs->KICK_REG0 = 0x83e70b13;
    //boot_cfg_regs->KICK_REG1 = 0x95a4f1e0;
    //����SDRAM��ʱ�Ĵ���(SDTIM1~SDTIM3)
    DDR_Regs->SDRAM_TIM_1   =/*11077823*/
        ((unsigned int)(13.5*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RP_SHIFT)|
        ((unsigned int)(13.5*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RCD_SHIFT)|
        ((unsigned int)(6*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_WR_SHIFT)|
        ((unsigned int)(36*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RAS_SHIFT)|
        ((unsigned int)(49.5*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RC_SHIFT)|
        ((unsigned int)(30*clock_MHz/(4*1000.f)-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RRD_SHIFT)|
        ((unsigned int)(6*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_WTR_SHIFT);
    DDR_Regs->SDRAM_TIM_2   = (5<<25)| /*ODTH8*/ /*4A4F7FDA*/
        ((5-1)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XP_SHIFT)|
        ((unsigned int)(120*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XSNR_SHIFT)|
        ((512-1)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XSRD_SHIFT)|
        ((unsigned int)(6*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_RTP_SHIFT)|
        ((3-1)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_CKE_SHIFT);
    DDR_Regs->SDRAM_TIM_3   = /*051F8498*/
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

 /****************************************************************
 * KeyStone_DDR_Init.c
 *
 * Created on: 2012-5-4
 *
 * Author: ZhangXiang
 *****************************************************************/

#include <stdio.h>
#include <csl_bootcfgAux.h>
#include "KeyStone_DDR_Init.h"

CSL_Emif4fRegs * DDR_Regs = (CSL_Emif4fRegs*) CSL_DDR3_EMIF_CONFIG_REGS;//0x21000000
CSL_BootcfgRegs * boot_cfg_regs = (CSL_BootcfgRegs*) CSL_BOOT_CFG_REGS;//0x02620000

void Shannon_EVM_DDR_Init(float clock_MHz)
{

	//CSL_Emif4fRegs * DDR_Regs = (CSL_Emif4fRegs*) CSL_DDR3_EMIF_CONFIG_REGS;
	//CSL_BootcfgRegs * boot_cfg_regs = (CSL_BootcfgRegs*) CSL_BOOT_CFG_REGS;

	printf("configure DDR at %d MHz\n", (unsigned int)clock_MHz);

	CSL_BootCfgUnlockKicker();
	//boot_cfg_regs->KICK_REG0 = 0x83e70b13;
	//boot_cfg_regs->KICK_REG1 = 0x95a4f1e0;

	//����SDRAM��ʱ�Ĵ���(SDTIM1~SDTIM3)
	DDR_Regs->SDRAM_TIM_1   =/*11077823*/
		((unsigned int)(13.5*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RP_SHIFT)|
		((unsigned int)(13.5*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RCD_SHIFT)|
		((unsigned int)(6*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_WR_SHIFT)|
		((unsigned int)(36*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RAS_SHIFT)|
		((unsigned int)(49.5*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RC_SHIFT)|
		((unsigned int)(30*clock_MHz/(4*1000.f)-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RRD_SHIFT)|
		((unsigned int)(6*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_WTR_SHIFT);
	DDR_Regs->SDRAM_TIM_2   = (5<<25)| /*ODTH8*/ /*4A4F7FDA*/
		((5-1)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XP_SHIFT)|
		((unsigned int)(120*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XSNR_SHIFT)|
		((512-1)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XSRD_SHIFT)|
		((unsigned int)(6*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_RTP_SHIFT)|
		((3-1)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_CKE_SHIFT);
	DDR_Regs->SDRAM_TIM_3   = /*051F8498*/
		((5)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_CSTA_SHIFT)|
		((64-1)<<CSL_EMIF4F_SDRAM_TIM_3_REG_ZQ_ZQCS_SHIFT)|
		((unsigned int)(110*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_RFC_SHIFT)|
		((9-1)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_RAS_MAX_SHIFT);

	DDR_Regs->DDR_PHY_CTRL_1  = 0x00100100|  /*0010010F*/
		(15<<CSL_EMIF4F_DDR_PHY_CTRL_1_REG_READ_LATENCY_SHIFT);

	/*This is a JEDEC requirement that we have 500us delay between reset de-assert
	and cke assert and then program the correct refresh rate
	The DDR internal clock is divide by 16 before SDCFG write*/
	DDR_Regs->SDRAM_REF_CTRL = 0x0000515C; //500 us

	DDR_Regs->ZQ_CONFIG =/*50074C1F*/
		((0)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_CS1EN_SHIFT)|
		((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_CS0EN_SHIFT)|
		((0)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_DUALCALEN_SHIFT)|
		((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_SFEXITEN_SHIFT)|
		((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_ZQINIT_MULT_SHIFT)|
		((3)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_ZQCL_MULT_SHIFT)|
		((0x4C1F)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_REFINTERVAL_SHIFT);

	/*map priority 0,1,2,3 to COS0,
	map priority 3,5,6,7 to COS1*/
	DDR_Regs->PRI_COS_MAP =/*80005500*/
		((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_COS_MAP_EN_SHIFT)|
		((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_7_COS_SHIFT)|
		((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_6_COS_SHIFT)|
		((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_5_COS_SHIFT)|
		((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_4_COS_SHIFT)|
		((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_3_COS_SHIFT)|
		((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_2_COS_SHIFT)|
		((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_1_COS_SHIFT)|
		((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_0_COS_SHIFT);

	/*master based COS map is disabled*/
	DDR_Regs->MSTID_COS_1_MAP= 0;
	DDR_Regs->MSTID_COS_2_MAP= 0;

	/*LAT_CONFIG*/
	DDR_Regs->VBUSM_CONFIG=/*00081020*/
		(8<<CSL_EMIF4F_VBUSM_CONFIG_REG_COS_COUNT_1_SHIFT)|
		(16<<CSL_EMIF4F_VBUSM_CONFIG_REG_COS_COUNT_2_SHIFT)|
		(32<<CSL_EMIF4F_VBUSM_CONFIG_REG_PR_OLD_COUNT_SHIFT);

	DDR_Regs->ECC_CTRL =
		((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_EN_SHIFT)|
		((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_PROT_SHIFT)|
		((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_2_EN_SHIFT)|
		((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_1_EN_SHIFT);

	DDR_Regs->SDRAM_CONFIG =/*63462a32*/
		(3<<CSL_EMIF4F_SDRAM_CONFIG_REG_SDRAM_TYPE_SHIFT)|
		(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_IBANK_POS_SHIFT)|
		(DDR_TERM_RZQ_OVER_6<<CSL_EMIF4F_SDRAM_CONFIG_REG_DDR_TERM_SHIFT)|
		(DDR_DYN_ODT_OVER_2<<CSL_EMIF4F_SDRAM_CONFIG_REG_DYN_ODT_SHIFT)|
		(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_DDR_DISABLE_DLL_SHIFT)|
		(SDRAM_DRIVE_RZQ_OVER_7<<CSL_EMIF4F_SDRAM_CONFIG_REG_SDRAM_DRIVE_SHIFT)|
		(DDR_CWL_7<<CSL_EMIF4F_SDRAM_CONFIG_REG_CWL_SHIFT)|
		(DDR_BUS_WIDTH_64<<CSL_EMIF4F_SDRAM_CONFIG_REG_NARROW_MODE_SHIFT)|
		(DDR_CL_9<<CSL_EMIF4F_SDRAM_CONFIG_REG_CL_SHIFT)|
		(DDR_ROW_SIZE_13_BIT<<CSL_EMIF4F_SDRAM_CONFIG_REG_ROWSIZE_SHIFT)|
		(DDR_BANK_NUM_8<<CSL_EMIF4F_SDRAM_CONFIG_REG_IBANK_SHIFT)|
		(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_EBANK_SHIFT)|
		(DDR_PAGE_SIZE_10_BIT_1024_WORD<<CSL_EMIF4F_SDRAM_CONFIG_REG_PAGESIZE_SHIFT);

	//initial vale for leveling

	boot_cfg_regs->DDR3_CONFIG_REG[14] = 0x3C;
	boot_cfg_regs->DDR3_CONFIG_REG[15] = 0x3C;
	boot_cfg_regs->DDR3_CONFIG_REG[16] = 0x23;
	boot_cfg_regs->DDR3_CONFIG_REG[17] = 0x2D;
	boot_cfg_regs->DDR3_CONFIG_REG[18] = 0x13;
	boot_cfg_regs->DDR3_CONFIG_REG[19] = 0x11;
	boot_cfg_regs->DDR3_CONFIG_REG[20] = 0x9;
	boot_cfg_regs->DDR3_CONFIG_REG[21] = 0xC;
	boot_cfg_regs->DDR3_CONFIG_REG[22] = 0x21;

	boot_cfg_regs->DDR3_CONFIG_REG[2] = 0x0;
	boot_cfg_regs->DDR3_CONFIG_REG[3] = 0x0;
	boot_cfg_regs->DDR3_CONFIG_REG[4] = 0x0;
	boot_cfg_regs->DDR3_CONFIG_REG[5] = 0x0;
	boot_cfg_regs->DDR3_CONFIG_REG[6] = 0x0;
	boot_cfg_regs->DDR3_CONFIG_REG[7] = 0x0;
	boot_cfg_regs->DDR3_CONFIG_REG[8] = 0x0;
	boot_cfg_regs->DDR3_CONFIG_REG[9] = 0x0;
	boot_cfg_regs->DDR3_CONFIG_REG[10] = 0x0;

	boot_cfg_regs->DDR3_CONFIG_REG[0] |= 0xF;
	boot_cfg_regs->DDR3_CONFIG_REG[23] |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS

	//enable full leveling, no incremental leveling
	/*Typically you program the ramp window for a higher rate of
	incremental leveling, meaning the 3 fields in the ramp control
	register will be smaller than the corresponding fields in the
	RDWR_LVL_CTRL.*/

	DDR_Regs->RDWR_LVL_RMP_WIN = 4096;/*0x00001000*/
	DDR_Regs->RDWR_LVL_RMP_CTRL =/*90000000*/
		(1<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_RDWRLVL_EN_SHIFT)|
		(16<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_RDWRLVLINC_RMP_PRE_SHIFT)|
		(0<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_RDLVLINC_RMP_INT_SHIFT)|
		(0<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_RDLVLGATEINC_RMP_INT_SHIFT)|
		(0<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_WRLVLINC_RMP_INT_SHIFT);
	DDR_Regs->RDWR_LVL_CTRL =/*A0000000*/
		(1<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_RDWRLVLFULL_START_SHIFT)|
		(32<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_RDWRLVLINC_PRE_SHIFT)|
		(0<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_RDLVLINC_INT_SHIFT)|
		(0<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_RDLVLGATEINC_INT_SHIFT)|
		(0<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_WRLVLINC_INT_SHIFT);

	//	DDR_Regs->SDRAM_REF_CTRL    = 64000000/8192/(1000/clock_MHz);

	DDR_Regs->SDRAM_REF_CTRL    = 64000.f*clock_MHz/8192.f;/*00001457*/

	CSL_BootCfgLockKicker();

	printf("DDR Initialization Passed!\n");
}

0 Bruce Chen1 13 年多前回复 Zhang Jerry

Expert 1775 points

您好！

关于KICK REG硬仿与软仿的差异，

硬仿的确是返回0，你只需往REG里写值，unlock即可。

软仿之所以显示，是CCS的BUG。

0 Zhang Jerry 13 年多前回复 Bruce Chen1

Prodigy 140 points

您好！

请问您说的硬仿返回值是0，是Kicker Mechanism Register解锁的情况还是锁住的情况呢？

我仿真时发现以下两种情况的返回值都是0

CSL_IDEF_INLINE void CSL_BootCfgUnlockKicker (void)

{

hBootCfg->KICK_REG0 = 0x83e70b13;

hBootCfg->KICK_REG1 = 0x95a4f1e0;

return;

}

和

CSL_IDEF_INLINE void CSL_BootCfgLockKicker (void)

{

hBootCfg->KICK_REG0 = 0x1;

hBootCfg->KICK_REG1 = 0x1;

return;

}

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6678 DDR初始化相关问题