AM437x工程样片上GPMC 访问FPGA异常

xing zhou1

在AM437x工程样片上基于startware，使用GPMC访问FPGA，访问映射空间时，FPGA检测不到片选和读写信号。请各位帮忙看看。

1：初始化代码如下：

void fpga_init(void)
{
    int32_t status = S_PASS;
    uint32_t baseAddr = SOC_GPMC_CONFIG_REG;
    uint32_t csNum = GPMC_CHIP_SEL_3;
    uint32_t i;

    /* Perform the Clock configurations for GPMC. */
   status = PRCMModuleEnable(CHIPDB_MOD_ID_GPMC, 0U, FALSE);

   /* Perform the Pinmux configurations for GPMC. */
   status = PINMUXModuleConfig(CHIPDB_MOD_ID_GPMC, 0U, NULL);

   // reset
   GPMCModuleReset(baseAddr);
   //wait reset done
   while (GPMCIsModuleResetDone(baseAddr) != TRUE);

#if 1
    GPMCChipSelEnable(baseAddr, csNum, FALSE);
    GPMCSetTimeParaGranularity(baseAddr, csNum, GPMC_TIME_GRANULARITY_X1);
   GPMCSetDevType(baseAddr, csNum, GPMC_DEV_TYPE_NOR);
   GPMCSetAddrDataMuxType(baseAddr, csNum, GPMC_MUX_TYPE_NONE);
   GPMCSetAccessMode(baseAddr, csNum, GPMC_OPER_MODE_READ, GPMC_ACCESS_MODE_SINGLE);//GPMC_ACCESS_MODE_MULTIPLE
   GPMCSetAccessMode(baseAddr, csNum, GPMC_OPER_MODE_WRITE, GPMC_ACCESS_MODE_SINGLE);
   GPMCSetAccessType(baseAddr, csNum, GPMC_ACCESS_TYPE_ASYNC_READ);
   GPMCSetAccessType(baseAddr, csNum, GPMC_ACCESS_TYPE_ASYNC_WRITE);
   GPMCSetChipSelBaseAddr(baseAddr, csNum, (FPGA_BASE>>24));
   GPMCSetChipSelMaskAddr(baseAddr, csNum, GPMC_MASK_ADDR_64MB);

   gpmcChipSelTiming.chipSelWrOffTime = 5;
   gpmcChipSelTiming.chipSelRdOffTime = 22;
   gpmcChipSelTiming.chipSelOnTime = 1;
   gpmcChipSelTiming.addExtDelay = TRUE;
   GPMCChipSelectTimingConfig(baseAddr, csNum, &gpmcChipSelTiming);

   gpmcAdvSignalTiming.advOnTime = 1;
   gpmcAdvSignalTiming.advRdOffTime = 22;
   gpmcAdvSignalTiming.advWrOffTime = 5;
   gpmcAdvSignalTiming.advAadMuxWrOffTime = 0U;
   gpmcAdvSignalTiming.advAadMuxRdOffTime = 0U;
   gpmcAdvSignalTiming.advAadMuxOnTime = 0U;
   gpmcAdvSignalTiming.addExtDelay = TRUE;
   GPMCAdvSignalTimingConfig(baseAddr, csNum, &gpmcAdvSignalTiming);

   gpmcOeWeSignalTiming.writeEnableOffTime = 5;
   gpmcOeWeSignalTiming.writeEnableOnTime = 0;
   gpmcOeWeSignalTiming.oeOffTime = 22;
   gpmcOeWeSignalTiming.oeOnTime = 0;
   gpmcOeWeSignalTiming.oeAadMuxOffTime = 0;
   gpmcOeWeSignalTiming.oeAadMuxOnTime = 0;
   gpmcOeWeSignalTiming.addExtDelay = TRUE;
   GPMCWeOeSignalTimingConfig(baseAddr, csNum, &gpmcOeWeSignalTiming);

   gpmcReadAccessTiming.readCycleTime = 22;
   gpmcReadAccessTiming.writeCycleTime = 5;
   gpmcReadAccessTiming.readAccessTime = 7 ;
   gpmcReadAccessTiming.pageBurstAccessTime = 2;
   GPMCReadAccessTimingConfig(baseAddr, csNum, &gpmcReadAccessTiming);

   gpmcCycle2CycleDelayTiming.cycle2CycleDelay = 2;
    gpmcCycle2CycleDelayTiming.cycleDelaySameChipSel = GPMC_CYCLE_DELAY_SAME_CHIP_SEL_DELAY;
    gpmcCycle2CycleDelayTiming.cycleDelayDiffChipSel = GPMC_CYCLE_DELAY_DIFF_CHIP_SEL_DELAY;
    gpmcCycle2CycleDelayTiming.busTurnAroundTime = 0U;
   GPMCCycleDelayTimingConfig(baseAddr, csNum, &gpmcCycle2CycleDelayTiming);

   GPMCWriteAccessTimingConfig(baseAddr, csNum, 2, 4);

   GPMCLimitedAddrSupportEnable(baseAddr, FALSE);

   GPMCChipSelEnable(baseAddr, csNum, TRUE);
#endif

#if 0
   /* Perform the GPMC configurations for FPGA. */
   if(S_PASS == status)
   {
       HWREG(baseAddr + GPMC_CONFIG7(3)) = 0;         //CS3 disable
       for(i=0;i<10000;i++);
       HWREG(baseAddr + GPMC_CONFIG1(3)) = 0x41001000;//0x40801000;//nor,16bit
       HWREG(baseAddr + GPMC_CONFIG2(3)) = 0x50501;//0x00040400;//cs timing
       HWREG(baseAddr + GPMC_CONFIG3(3)) = 0x0;
       HWREG(baseAddr + GPMC_CONFIG4(3)) = 0x02020202;//0x05801680;//we oe timing
       HWREG(baseAddr + GPMC_CONFIG5(3)) = 0x04050505;//0x02070516; //rd wr timing
       HWREG(baseAddr + GPMC_CONFIG6(3)) = 0x1c1;//0x020402c2;//cycle2cycle timing
       HWREG(baseAddr + GPMC_CONFIG7(3)) = ((GPMC_CONFIG7_MASKADDRESS_SIZE64MB << 8) | ((FPGA_BASE >> 24) & 0x3F) | (1 << 6));    //CS6 enable
       for(i=0;i<10000;i++);

       HWREG(baseAddr + GPMC_CONFIG7(1)) = 0;         //CS1 disable
       HWREG(baseAddr + GPMC_CONFIG7(2)) = 0;         //CS2 disable
       //HWREG(baseAddr + GPMC_CONFIG7(3)) = 0;         //CS3 disable
       HWREG(baseAddr + GPMC_CONFIG7(4)) = 0;         //CS4 disable
       HWREG(baseAddr + GPMC_CONFIG7(5)) = 0;         //CS5 disable
       HWREG(baseAddr + GPMC_CONFIG7(6)) = 0;         //CS6 disable

       HWREG(baseAddr + GPMC_CONFIG) &= ~0x2;         // 打开A11

   }
#endif

}

2：头文件如下：

/*
* drv_fpga.h
*
* Created on: 2015年8月20日
* Author: Administrator
*/

#ifndef DRV_FPGA_H_
#define DRV_FPGA_H_

#define FPGA_BASE 0x4000000
#define FPGA_SPACE 0x4000000

extern void fpga_init(void);

#endif /* DRV_FPGA_H_ */

3：访问FPGA代码：

    CACHEDataCleanAll();
    for(tt =64 ;tt<128;tt++)
    {
       fpgatest = (volatile uint32_t *)(tt<<20);
       CONSOLEUtilsPrintf("\n\rread data : %d. at addr %x.\n\r", *fpgatest,fpgatest);
    }

10 年多前